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shock detector flash mcu HT45F56 revision: v1.11 date: april 11, 2017
rev. 1.11 2 april 11, 2017 rev. 1.11 3 april 11, 2017 HT45F56 shock detector flash mcu HT45F56 shock detector flash mcu table of contents eates cpu features ......................................................................................................................... 5 peripheral f eatures ................................................................................................................. 5 general description ......................................................................................... 6 block diagram .................................................................................................. 6 pin assignment ........... ..................................................................................... 6 pin descriptions .............................................................................................. 7 absolute maximum ratings ............................................................................ 8 d.c. characteristics ......................................................................................... 8 a.c. characteristics ......................................................................................... 9 lvr electrical characteristics ...................................................................... 10 comparator electrical characteristics ........................................................ 10 r-2r d/a converter electrical characteristics ........................................... 10 shock sensor amplifer electrical characteristics clockin g and pipelining ......................................................................................................... 12 program counter ................................................................................................................... 13 stack ..................................................................................................................................... 14 arithme tic and logic unit C alu ........................................................................................... 14 flash program memory ................................................................................. 15 structure ................................................................................................................................ 15 special vectors ..................................................................................................................... 15 look-up table ............. ........................................................................................................... 15 table program example ........................................................................................................ 16 in circuit programming C icp ............................................................................................... 17 on-chip d ebug support C ocds ......................................................................................... 18 data memory .................................................................................................. 18 structure ................................................................................................................................ 18 general purpose data memory ............................................................................................ 19 special purpo se data memory ............................................................................................. 19 special function register description ........................................................ 20 indirect addressing re gisters C iar0, iar1 ......................................................................... 20 memory pointers C mp0, mp1 .............................................................................................. 20 bank pointer C bp ................................................................................................................. 21 accumulator C acc ............................................................................................................... 21 program counter low register C pcl .................................................................................. 21 look-up table registers C tblp, tblh ................................................................................ 21 status register C status .................................................................................................... 22
rev. 1.11 2 april 11, 2017 rev. 1.11 3 april 11, 2017 HT45F56 shock detector flash mcu HT45F56 shock detector flash mcu eeprom data memory ........... ....................................................................... 24 eeprom data memory structure ........................................................................................ 24 eeprom registers ............ .................................................................................................. 24 reading data from the eeprom ......................................................................................... 26 writing data to the eeprom ................................................................................................ 26 write protection ..................................................................................................................... 26 eeprom interrupt ............. ................................................................................................... 26 programming considerations ............. ................................................................................... 27 oscillator ........................................................................................................ 28 oscillator overview ............. .................................................................................................. 28 system clock confgurations ................................................................................................ 28 internal high speed rc oscillator C hirc ........................................................................... 29 internal 32khz oscillator C lirc ........................................................................................... 29 supplementary oscillators .................................................................................................... 29 operating modes and system clocks ......................................................... 29 system clocks ...................................................................................................................... 29 system operation modes ...................................................................................................... 30 control registers .................................................................................................................. 31 operating mode switching .................................................................................................... 33 standby current considerations ........................................................................................... 37 wake-up ................................................................................................................................ 37 watchdog timer ........... .................................................................................. 38 watchdog timer clock source .............................................................................................. 38 watchdog timer control register ............. ............................................................................ 38 watchdog timer operation ................................................................................................... 39 reset and initialisation .................................................................................. 40 reset functions ............. ....................................................................................................... 40 reset initial conditions ......................................................................................................... 45 input/output ports ......................................................................................... 47 pull-high resistors ................................................................................................................ 47 port a wake-up ............. ........................................................................................................ 48 i/o port control register ....................................................................................................... 48 pin-shared functions ............. ............................................................................................... 48 i/o pin structures .................................................................................................................. 49 programming considerations ............. ................................................................................... 50 compact type timer module C ctm .......... .................................................. 51 compact tm operation ......................................................................................................... 52 compact type tm register description ................................................................................ 52 compact type tm operation modes .................................................................................... 56 programming considerations ............. ................................................................................... 62
rev. 1.11 4 april 11, 2017 rev. 1.11 5 april 11, 2017 HT45F56 shock detector flash mcu HT45F56 shock detector flash mcu digital to analog converter .......... ................................................................ 63 operational amplifer .................................................................................... 64 comparators .................................................................................................. 65 comparator operation .......................................................................................................... 65 comparator registers ........................................................................................................... 65 interrupts ........................................................................................................ 67 interrupt registers ................................................................................................................. 67 interrupt operation ................................................................................................................ 69 comparator interrupt ............................................................................................................. 70 debounce interrupt ............................................................................................................... 71 time base interrupt ............................................................................................................... 71 eeprom interrupt ............. ................................................................................................... 72 tm interrupts ......................................................................................................................... 72 interrupt wake-up function ................................................................................................... 73 programming considerations ............. ................................................................................... 73 application circuits ........... ............................................................................ 74 sense magnetic sensor module signal by sen pin ............................................................. 74 instruction set ................................................................................................ 75 introduction ........................................................................................................................... 75 instruction timing .................................................................................................................. 75 moving and transferring data ............................................................................................... 75 arithmetic operations ............................................................................................................ 75 logical and rotate operation ............................................................................................... 76 branches and control transfer ............................................................................................. 76 bit operations ....................................................................................................................... 76 table read operations ......................................................................................................... 76 other operations ............. ...................................................................................................... 76 instruction set summary .......... .................................................................... 77 table conventions ................................................................................................................. 77 instruction defnition ..................................................................................... 79 package information ..................................................................................... 88 8-pin sop (150mil) outline dimensions ............................................................................... 89
rev. 1.11 4 april 11, 2017 rev. 1.11 5 april 11, 2017 HT45F56 shock detector flash mcu HT45F56 shock detector flash mcu features cpu features ? operating v oltage: f sys = 8mhz : 2.2v~5.5v ? up to 0.5s instruction cycle with 8mhz system clock at v dd =5v ? power down and wake-up functions to reduce power consumption ? oscillator t ypes internal high speed rc C hirc internal 32khz rc C lirc ? fully integrated internal 8mhz oscillator requires no external components ? multi-mode operation: normal, slow, idle and sleep ? all instructions executed in one to three instruction cycles ? table read instructions ? 63 powerful instructions ? 2-level subroutine nesting ? bit manipulation instruction peripheral features ? program memory: 1k 14 ? data memory: 32 8 ? true eeprom memory: 32 8 ? watchdog t imer function ? 6 bidirectional i/o lines ? multiple t imer modules for time measure, input capture, compare match output, pwm output function or single pulse output function ? one comparator with hysteresis control and interrupt generation ? one operational amplifer with gain control ? one 6-bit d/a converter ? debounce circuit for comparator output with interrupt generation ? dual t ime-base functions for generation of fxed time interrupt signals ? low voltage reset function ? flash program memory can be re-programmed up to 100,000 times ? flash program memory data retention > 10 years ? true eeprom data memory can be re-programmed up to 1,000,000 times ? true eeprom data memory data retention > 10 years ? package types: 8-pin sop
rev. 1.11 6 april 11, 2017 rev. 1.11 7 april 11, 2017 HT45F56 shock detector flash mcu HT45F56 shock detector flash mcu general description the device is a flash memory type 8-bit high performance risc architecture microcontroller with fully integrated shock sensor which is designed for various product applications. of fering users the convenience of flash memory mult i-programming features, the dvice also includes a wide range of functions amd features. in addition to the fash program memory , other memory includes areas of ram data memory and true eeprom data memory. analog f eatures i nclude a 6 -bit dac , a c omparator a nd a n op erational am plifier. mu ltiple a nd extremely fexible t imer modules provide timing, pulse generation and pwm generation functions. the inclusion of fexible i/o programming features, t ime base functions together with many other features further enhance device functionality. protective features such as an internal w atchdog t imer and l ow v oltage re set c oupled wi th e xcellent noi se i mmunity a nd e sd prot ection e nsure t hat reliable operation is maintained in hostile electrical environments. a full choice of hirc and lirc oscillator functions are provided including a fully integrated system oscillator. the ability to operate and switch dynamically between a range of operating modes using different clock sources gives users the ability to optimise microcontroller operation and minimise power consumption. block diagram 8-bit risc mcu core i/o timer modules flash program memory eeprom data memory flash/eeprom programming circuitry time base low voltage reset watchdog timer interrupt controller reset circuit ram data memory h.w. debounce internal hirc oscillator operational amplifier internal lirc oscillator comparator 6-bit d/a converter pin assignment pa 2/ ctck / icpck vdd pa 1/ ad 1 1 2 3 4 8 7 6 5 pa 6/ ad 2 pa 5/ sen pa 0/ ctp / icpda vss pa7/ res ht 45f 56 8 sop -a 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 pa 2/ ctck / icpck vdd pa 1/ ad 1 pa 6/ ad 2 pa 5/ sen pa 0/ ctp / icpda vss nc nc nc ocdsck nc nc nc ocdsda pa7/ res ht 45v 56 16 nsop -a note: the ocdsda and ocdsck pins are the ocds dedicated pins and only available for the ht45v56 device which is the ocds ev chip for the HT45F56 device.
rev. 1.11 6 april 11, 2017 rev. 1.11 7 april 11, 2017 HT45F56 shock detector flash mcu HT45F56 shock detector flash mcu pin descriptions with the exceptio n of the power pins and some relevant transformer control pins, all pins on these devices can be referenced by their port name, e.g. p a.0, p a.1 etc, which refer to the digital i/o function of the pins. however these port pins are also shared with other function such as the analog to digital converter, t imer module pins etc. t he function of each pin is listed in the following table, however the details behind how each pin is confgured is contained in other sections of the datasheet. pad name function opt i/t o/t description pa0/ctp/icpda pa0 pawu papu psel st cmos general purpose i/o. register enabled pull-up and wake-up. ctp psel cmos ctm output icpda st cmos icp data/address pin pa1/ad1 pa1 pawu papu psel st cmos general purpose i/o. register enabled pull-up and wake-up. ad1 psel an threshold adjustment input pa2/ctck/icpck pa2 pawu papu psel st cmos general purpose i/o. register enabled pull-up and wake-up. ctck st ctm clock input icpck st cmos icp clock pin pa5/sen pa5 pawu papu psel st cmos general purpose i/o. register enabled pull-up and wake-up. sen psel an shock sensor analog input pa6/ad2 pa6 pawu papu psel st cmos general purpose i/o. register enabled pull-up and wake-up. ad2 psel an threshold adjustment input pa7/ res pa7 papu psel st cmos general purpose i/o. register enabled pull-up and wake-up. res rstc st external reset input ocdsda ocdsda st cmos ocds data/address pin, for ev chip only. ocdsck ocdsck st ocds clock pin, for ev chip only. vdd vdd pwr positive power supply vss vss pwr negative power supply, ground. legend: i/t: input type o/t: output type opt: optional by confguration option (co) or register option st: schmitt t rigger input cmos: cmos output an: analog input pwr: power
rev. 1.11 8 april 11, 2017 rev. 1.11 9 april 11, 2017 HT45F56 shock detector flash mcu HT45F56 shock detector flash mcu absolute maximum ratings supply v oltage .............. .................................................................................. v ss ?0.3v to v ss +6.0v input v oltage .............. .................................................................................... v ss ? 0.3v to v dd +0.3v storage t emperature ............... ..................................................................................... -50? c to 125?c operating t emperature .............. .................................................................................... -40? c to 85 ?c i ol t otal .............. ................................................................................................... .................... 80ma i oh t otal .............. ...................................................................................................................... -80ma total power dissipation .............. ........................................................................................... 500mw note: t hese a re st ress ra tings onl y. st resses e xceeding t he ra nge spe cified und er "absol ute ma ximum ratings" m ay c ause su bstantial d amage t o t hese d evices. fu nctional o peration o f t hese d evices a t other c onditions be yond t hose l isted i n t he spe cifcation i s no t i mplied a nd pr olonged e xposure t o extreme conditions may affect devices reliability. d.c. characteristics ta=25 c symbol parameter test conditions min. typ. max. unit v dd conditions v dd operating voltage (hirc) f f sys =8mhz v lvr f 5.5 v i dd operating current (hirc) 3v f sys =f h =8mhz no load, all peripherals off f 1.1 1.7 5v f 2.9 4.4 ma 3v f sys =f h /2 no load, all peripherals off f 1.1 1.6 ma 5v f 1.8 3.0 ma 3v f sys =f h /4 no load, all peripherals off f 1.0 1.6 ma 5v f 1.7 2.8 ma 3v f sys =f h /8 no load, all peripherals off f 1.0 1.5 ma 5v f 1.5 2.5 ma 3v f sys =f h /16 no load, all peripherals off f 0.9 1.4 ma 5v f 1.4 2.2 ma 3v f sys =f h /32 no load, all peripherals off f 0.8 1.2 ma 5v f 1.3 2.0 ma 3v f sys =f h /64 no load, all peripherals off f 0.8 1.1 ma 5v f 1.1 1.7 ma operating current (lirc) 3v f sys =f sub =f lirc =32khz no load, all peripherals off f 40 60 5v f 90 135 i stb standby current (idle0 mode) 3v f sys off, f sub on no load, all peripherals off f 3 5 5v f 5 10 standby current (idle1 mode) 3v f sys =f hirc =8mhz on, f sub on no load, all peripherals off f 0.8 1.6 ma 5v f 1.0 2.0 ma standby current (sleep0 mode) 3v lirc off, wdt disable no load, all peripherals off f 0.1 1.0 5v f 0.3 2.0 standby current (sleep1 mode) 3v lirc on, wdt enable no load, all peripherals off f 1.3 5.0 5v f 2.2 10.0 v il input low voltage for i/o ports or input pins except res pin 5v f 0 f 1.5 v f f 0 f 0.2v dd v input low voltage for res pin f f 0 f 0.4v dd v
rev. 1.11 8 april 11, 2017 rev. 1.11 9 april 11, 2017 HT45F56 shock detector flash mcu HT45F56 shock detector flash mcu symbol parameter test conditions min. typ. max. unit v dd conditions v ih input high voltage for i/o ports or input pins except res pin 5v 3.5 5.0 v 0.8v dd v dd v input high voltage for res pin 0.9v dd v dd v i ol sink current for i/o port 3v v ol = 0.1v dd 8 16 ma 5v 16 32 ma i oh source current for i/o port 3v v oh = 0.9v dd -4.0 -8.0 ma 5v -8.0 -16.0 ma r ph pull-high resistance for i/o ports 3v 20 60 100 k 5v 10 30 50 k a.c. characteristics ta=25c symbol parameter test condition min. typ. max. unit v dd condition f sys system clock (hirc) 2.2~5.5v f sys =f hirc =8mhz 8 mhz system clock (lirc) 2.2~5.5v f sys =f lirc =32khz 32 khz f hirc high speed internal rc oscillator (hirc) 3v/5v ta=25c -2% 8 +2% mhz 3v/5v ta=0c ~ 70c -5% 8 +5% mhz 2.2v~5.5v ta=0c ~ 70c -8% 8 +8% mhz 2.2v~5.5v ta= -40c to 85c -12% 8 +12% mhz f lirc low speed internal rc oscillator (lirc) 2.2v~5.5v ta= -40c to 85c 4 32 80 khz t tck ctck pin minimum input pulse width 0.3 s t res external reset minimum input pulse width 10 s t sst system start-up timer period (wake-up from power down mode and f sys off) f sys =f h =f hirc 16 t hirc f sys =f sub =f lirc 2 t lirc system start-up timer period (wake-up from power down mode and f sys on) f sys =f h =f hirc 2 t h f sys =f sub =f lirc 2 t sub t rstd system reset delay time (power-on reset, lvr hardware reset, wdtc/rstc software reset) 25 50 150 ms system reset delay time (res reset / wdt hardware reset) 8.3 16.7 50 ms t eerd eeprom read time 4 t sys t eewr eeprom write time 3 6 ms 1rwh w sys i sys . dd dud i ud du iu d s dsdu 9 d 9 d d d y d s
rev. 1.11 10 april 11, 2017 rev. 1.11 11 april 11, 2017 HT45F56 shock detector flash mcu HT45F56 shock detector flash mcu lvr electrical characteristics ta=25c symbol parameter test conditions min. typ. max. unit v dd conditions v lvr low voltage reset voltage lvr enable, voltage select 2.1v - 5% 2.1 + 5% v t bgs v bg turn on stable time no load 150 s t lvr minimum low voltage width to reset 120 240 625 s comparator electrical characteristics ta=25c symbol parameter test conditions min. typ. max. unit v dd conditions v dd operating voltage 4.5 5.5 v v cm common mode voltage v ss v dd - 1.4 v v os input offset voltage -15 15 mv i cmp additional current consumption for comparator enabled 5v 100 130 a i pd power down current comparator disabled 0.1 a t rp response time 5v with 100mv overdrive, c load =3pf 2 s r-2r d/a converter electrical characteristics ta=25c symbol parameter test conditions min. typ. max. unit v dd conditions v dd operating voltage 4.5 5.5 v i dac additional current consumption for d/a converter enabled 5v 200 250 a dnl differential non-linearity 5v 0.5 lsb inl integral non-linearity 5v 1 lsb r o r-2r output resistor 5v 20 k shock sensor amplifer electrical characteristics ta=25c symbol parameter test conditions min. typ. max. unit v dd conditions v dd operating voltage 4.5 5.5 v v in inpuit voltage 5v 300 mv r s sample rate 5v 12 khz a v dc gain 5v 1.0 v/mv f in input frequency 5v 0 1.6 khz i opa additional current consumption for amplifer enabled 5v 500 a i pd power down current amplifer disabled 2 a
rev. 1.11 10 april 11, 2017 rev. 1.11 11 april 11, 2017 HT45F56 shock detector flash mcu HT45F56 shock detector flash mcu debounce circuit electrical characteristics ta=25c symbol parameter test conditions min. typ. max. unit v dd conditions v dd operating voltage 4.5 5.5 v t deb debounce time 5v dstag[2:0]=001b 0.0575 0.125 0.255 ms dstag[2:0]=010b 0.12 0.25 0.505 ms dstag[2:0]=011b 0.245 0.5 1.005 ms dstag[2:0]=100b 0.495 1.0 2.005 ms dstag[2:0]=101b 0.995 2.0 4.005 ms dstag[2:0]=110b 1.995 4.0 8.005 ms dstag[2:0]=111b 1.995 4.0 8.005 ms power-on reset characteristics ta = 25c symbol parameter test conditions min. typ. max. unit v dd conditions v por v dd start voltage to e nsure power-on reset 100 mv rr por v dd rising rate to ensure power-on reset 0.035 v/ms t por minimum time for v dd stays at v por to ensure power-on reset 1 ms
rev. 1.11 12 april 11, 2017 rev. 1.11 13 april 11, 2017 HT45F56 shock detector flash mcu HT45F56 shock detector flash mcu system architecture a key factor in the high-performan ce features of the holtek range of microcontrollers is attributed to their internal system architecture. the range of devices take advantag e of the usual features found within ris c microcontrollers providing increas ed s peed of operation and enhanced performance. the pi pelining sc heme i s i mplemented i n suc h a wa y t hat i nstruction fe tching a nd i nstruction execution a re ove rlapped, he nce i nstructions a re e ffectively e xecuted i n one c ycle, wi th t he exception of branch or call instructions. an 8-bit wide alu is used in practically all instruction set operations, which carries out arithm etic operations, logic operations, rotation, increment, decrement, branch decisions, etc. the internal data path is simplifed by moving data through the accumulator and the alu. certain internal registers are implemented in the data memory and can be directly or indirectly addresse d. the simple addressi ng methods of these registers along with additi onal architectural features ensure that a minimum of external components is required to provide a functional i/ o a nd a/ d c ontrol syst em wi th m aximum re liability a nd fe xibility. t his m akes t hese devices suitable for low-cost, high-volume production for controller applications. clocking and pipelining the main system clock, derived from either a hirc or lirc oscillator is subdivided into four internally generated non-overlapping clocks, t1~t4. the program counter is incremented at the beginning of the t1 clock during which time a new instruction is fetched. the remaining t2~t4 clocks carry out the decoding and execution functions. in this way , one t1~t4 clock cycle forms one instruction cycle. although the fetching and execution of instructio ns takes place in consecutive instruction c ycles, t he pi pelining st ructure of t he m icrocontroller e nsures t hat i nstructions a re effectively executed in one instruction cycle. the exception to this are instructions where the contents of the program counter are changed, such as subroutine calls or jumps, in which case the instruction will take one more instruction cycle to execute. for instructions involving branches, such as jump or call instructions, two machine cycles are required to complete instruction execution. an extra cycle is required as the program takes one cycle t o frst obt ain t he a ctual j ump or c all a ddress a nd t hen a nother c ycle t o a ctually e xecute t he branch. the requirement for this extra cycle should be taken into accou nt by programmers in timing sensitive applications. fetch inst. (pc) (system clock) f sys phase clock t1 phase clock t2 phase clock t3 phase clock t4 program counter pc pc+1 pc+2 pipelining execute inst. (pc-1) fetch inst. (pc+1) execute inst. (pc) fetch inst. (pc+2) execute inst. (pc+1) system clocking and pipelining
rev. 1.11 12 april 11, 2017 rev. 1.11 13 april 11, 2017 HT45F56 shock detector flash mcu HT45F56 shock detector flash mcu fetch inst. 1 1 mov a,[12h] 2 call delay 3 cpl [12h] 4 : 5 : 6 delay: nop execute inst. 1 fetch inst. 2 execute inst. 2 fetch inst. 3 flush pipeline fetch inst. 6 execute inst. 6 fetch inst. 7 instruction featching program counter during pro gram e xecution, t he progr am co unter i s use d t o ke ep t rack of t he a ddress of t he next instruction to be executed. it is automatically incremented by one each time an instruction is executed except for instructions, such as jmp or call that demand a jump to a non- consecutive program memory address. only the lower 8 bits, known as the program counter low register, are directly addressable by the application program. when execut ing instructi ons re quiring jumps to non-consecutive addresses such as a jump instruction, a subrout ine c all, i nterrupt or re set, e tc., t he m icrocontroller m anages progra m c ontrol by loading the required address into the program counter . for conditional skip instructions, once the condition has been met, the next instruction, which has already been fetched during the present instruction execut ion, is discarded and a dummy cycle takes its place while the correct instruction is obtained. program counter high byte low byte (pcl) pc9~pc8 pc7~pc0 program counter the lower byte of the program counter , known as the program counter low register or pcl, is available for program control and is a readable and writeable register . by transferring data directly into t his r egister, a sh ort p rogram j ump c an b e e xecuted d irectly; h owever, a s o nly t his l ow b yte is available for manipulation, the jumps are limited to the present page of memory that is 256 locations. when such program jumps are executed it should also be noted that a dummy cycle will be inserted. manipulating the pcl register may cause program branching, so an extra cycle is needed to pre-fetch.
rev. 1.11 14 april 11, 2017 rev. 1.11 15 april 11, 2017 HT45F56 shock detector flash mcu HT45F56 shock detector flash mcu stack this is a special part of the memory which is used to save the contents of the program counter only. the stack has multiple levels and is neither part of the data nor part of the program space, and is neither readable nor writeable. the activated level is indexed by the stack pointer , and is neither readable nor writeable. at a subroutine call or interrupt acknowledge signal, the contents of the program counter are pushed onto the stack. at the end of a subroutine or an interrupt routine, signaled by a return instruction, ret or reti, the program counter is restored to its previous value from the stack. after a device reset, the stack pointer will point to the top of the stack. if the stack is full and an enabled interrupt takes place, the interrupt request fag will be recorded but the acknowledge signal will be inhibited. when the stack pointer is decremented, by ret or reti, the interrupt will be serviced. this feature prevents stack overfow allo wing the programmer to use the struct ure more easily . however , when the stack is full, a call subroutine instruction can still be execu ted which will result in a stack overfow . precautions should be taken to avoid such cases which might cause unpredictable program branching. if the stack is overfow, the frst program counter save in the stack will be lost. stack pointer stack level 2 stack level 1 program memory program counter bottom of stack top of stack arithmetic and logic unit C alu the arith metic-logic unit or alu is a critical area of the microcontrol ler that carries out arithmetic and logic operations of the instructi on set. connected to the main micro controller data bus, the alu receives related ins truction codes and performs the required arithmetic or logical operations after which the result will be placed in the specifed register . as these alu calculation or operations may result in carry , borrow or other status changes, the status register will be correspondingly updated to refect these changes. the alu supports the following functions: ? arithmetic operations: add, addm, adc, adcm, sub, subm, sbc, sbcm, daa ? logic operations: and, or, xor, andm, orm, xorm, cpl, cpla ? rotation: rra, rr, rrca, rrc, rla, rl, rlca, rlc ? increment and decrement: inca, inc, deca, dec ? branch decision: jmp, sz, sza, snz, siz, sdz, siza, sdza, call, ret, reti
rev. 1.11 14 april 11, 2017 rev. 1.11 15 april 11, 2017 HT45F56 shock detector flash mcu HT45F56 shock detector flash mcu flash program memory the program memory is the location where the user code or program is stored. for the device the program memory is flash type, which means it can be programmed and re-programmed a lar ge number o f t imes, a llowing t he u ser t he c onvenience o f c ode m odification o n t he sa me d evice. by using the appropriate programming tools, these flash devices of fer users the flexibility to conveniently debug and develop their applications while also of fering a means of feld programming and updating. structure the progra m me mory ha s a c apacity of 1k14 bi ts. t he progra m me mory i s a ddressed by t he program counter and also contains data, table information and interrupt entries. t able data, which can be setup in any location within the program memory , is addressed by a separate table pointer registers. 000h 004h 01ch n00h nffh initialisation vector 14 bits interrupt vectors look-up table 020h 3ffh program memory structure special vectors within the program memory , certai n locations are reserved for the reset and interrupts. the location 000h is reserved for use by these devices reset for program initialisation. after a device reset is initiated, the program will jump to this location and begin execution. look-up table any location within the program memory can be defned as a look-up table where programmers can store fxed data. t o use the look-up table, the table pointer must frst be setup by placing the address of the look up data to be retrieved in the table pointer register , tblp and tbhp . these registers defne the total address of the look-up table. after se tting u p t he t able p ointer, t he t able d ata c an b e r etrieved f rom t he pr ogram me mory u sing the t abrd [m] or t abrdl [m] instructions respectively when the instruction is executed, the lower order table byte from the program memory will be transferred to the user defined data me mory r egister [ m] a s sp ecified i n t he i nstruction. t he h igher o rder t able d ata b yte f rom the program memory will be transferred to the tblh special register . any unused bits in this transferred higher order byte will be read as 0.
rev. 1.11 16 april 11, 2017 rev. 1.11 17 april 11, 2017 HT45F56 shock detector flash mcu HT45F56 shock detector flash mcu the accompanying diagram illustrates the addressing data fow of the look-up table. last page or pc high byte address tblp register data 14 bits program memory register tblh user selected register high byte low byte table program example the accompanying example shows how the table pointer and table data is defned and retrieved from the devic e. this example uses raw table data located in the last page which is stored there using the org statement. the value at this org statement is 300h which refers to the start address of the last page within the 1k program memory of the device. the table pointer low byte register is setup here to have an initial value of 06h. this will ensure that the frst data read from the data table will be at the program memory address 306h or 6 locations after the start of the last page. note that the value for the table pointer is referenced to the frst address of the present page if the tabrd [m] instruction is being used. the high byte of the table data which in this case is equal to zero will be transferred to the tblh register automatically when the tabrd [m] instruction is executed. because the tblh register is a read-only register and cannot be res tored, care should be taken to ensure its protection if both the main routine and interrupt s ervice routine us e table read instructions. if using the table read instructions, the interrupt service routines may change the value of the tblh and subsequently cause errors if used again by the main routine. as a rule it is recommended that simultaneous use of the table read instructions should be avoided. however , in situations where simultaneous use cannot be avoided, the interrupts should be disabled prior to the execution of any main routine table-read instructions. note that all table related instructions require two instruction cycles to complete their operation. table read program example tempreg1 db ? ; temporary register #1 tempreg2 db ? ; temporary register #2 : mov a,06h ; initialise low table pointer - note that this address is referenced mov tblp,a ; to the last page or current page : tabrd tempreg1 ; transfers value in table referenced by table pointer data at program ; memory address 306h transferred to tempreg1 and tblh dec tblp ; reduce value of table pointer by one tabrd tempreg2 ; transfers value in table referenced by table pointer data at program ; memory address 305h transferred to tempreg2 and tblh in this ; example the data 1ah is transferred to tempreg1 and data 0fh to ; register tempreg2 : org 300h ; sets initial address of program memory dc 00 ah, 00bh, 00ch, 00dh, 00eh, 00fh, 01ah, 01bh :
rev. 1.11 16 april 11, 2017 rev. 1.11 17 april 11, 2017 HT45F56 shock detector flash mcu HT45F56 shock detector flash mcu in circuit programming C icp the p rovision o f fl ash t ype pr ogram me mory p rovides t he u ser wi th a m eans o f c onvenient a nd easy upgrades and modifcations to their programs on the same device. as an additional convenience, holtek has provided a means of programming the microcontroller in- circuit using a 4-pin interface. this provides manufacturers with the possibility of manufacturing their circuit boards complete with a programmed or un-programmed microcontroller , and then programming o r u pgrading t he p rogram a t a l ater st age. t his enables product m anufacturers to e asily keep thei r manufa ctured products supplied with the latest program releases without removal and re- insertion of the device. holtek writer pins mcu programming pins pin description icpda pa0 programming serial data/address icpck pa2 programming clock vdd vdd power supply vss vss ground the program memory and eeprom data memory can be programmed serially in-circuit using this 4-wire interface. data is downloaded and uploaded serially on a single pin with an additional line for the clock. t wo additional lines are required for the power supply . the technical details regarding the in-cir cuit programming of the device are beyond the scope of this document and will be supplied in supplementary literature. during the programming process, the user must take care of the icpda and icpck pins for data and clock programming purposes to ensure that no other outputs are connected to these two pins.
note: * may be resistor or capacito r. the resistance of * must be great er than 1k or the capacitance of * must be less than 1nf.
rev. 1.11 18 april 11, 2017 rev. 1.11 19 april 11, 2017 HT45F56 shock detector flash mcu HT45F56 shock detector flash mcu on-chip debug support C ocds there is an ev chip named ht45v56 which is used to emulate the real mcu device named HT45F56. the ev chip device also provides the on-chip debug function to debug the real mcu device during development process. the ev chip and real mcu devices, ht45v56 and HT45F56, are almost functional compatible except the on-chip debug function. users can use the ev chip device to emulate the real mcu device behaviors by connecting the ocdsda and ocdsck pins to t he ho ltek ht -ide d evelopment t ools. t he oc dsda p in i s t he oc ds da ta/address i nput/output pin while the ocdsck pin is the ocds clock input pin. for more detailed ocds information, refer to the corresponding document named holtek e-link for 8-bit mcu ocds users guide. holtek e-link pins ev chip ocds pins pin description ocdsda ocdsda on-chip debug support data/address input/output ocdsck ocdsck on-chip debug support clock input vdd vdd power supply vss vss ground data memory the dat a mem ory is an 8-bit wide ram inte rnal me mory and is the loca tion where te mporary information is stored. structure divided into two types, the frst of data memory is an area of ram where special function registers are located. these registers have fixed locations and are necessary for correct operation of the device. m any of these registers can be read from and w ritten to directly under program control, however, some remain protected from user manipulation. the second area of data memory is reserved for general purpose use. all locations within this area are read and write accessible under program control. the overall data memory is subdivided into two banks. the special purpose data memory registers are accessible in all banks, with the exception of the eec register at address 40h, which is only accessible in bank 1. switching between the dif ferent data memory banks is achieved by setting the bank pointer to the correct value. the start address of the data memory for all devices is the address 00h. 00h 3fh 40h 5fh special purpose data memory general purpose data memory bank 0 eec@40h in bank 1 data memory structure
rev. 1.11 18 april 11, 2017 rev. 1.11 19 april 11, 2017 HT45F56 shock detector flash mcu HT45F56 shock detector flash mcu general purpose data memory all microcontroller programs require an area of read/write memory where temporary data can be stored and retrieve d for use later . it is this area of ram memory that is known as general purpose data memory . this area of data memory is fully accessible by the user programing for both reading and wr iting o perations. b y u sing t he b it o peration i nstructions i ndividual b its c an b e se t o r r eset under program control giving the user a lar ge range of fexibility for bit manipulation in the data memory. special purpose data memory this area of data memory is where registers, necessary for the correct operation of the microcontroller, are stored. most of the registers are both readable and writeable but some are protected and are readable only , the details of which are located under the relevant special function register section. note that for locat ions that are unused, any read instruction to these addresses will return the value 00h. 00h iar0 01h mp0 02h iar1 03h mp1 04h 05h acc 06h pcl 07h tblp 08h tblh 09h 0ah status 0bh 0ch 0dh 0eh 0fh 10h intc0 11h 12h 19h papu 18h pawu 1bh 1ah 1dh 1ch 1fh pa pac 13h 14h 15h 16h 17h : unused, read as 00h tbc 1eh eec bank 0 ~ bank 1 bp smod intc1 wdtc smod1 eea eed 20h 21h 22h 29h 28h 2bh 2ah 2dh 2ch 2fh 2eh 23h 24h 25h 26h 27h 30h 31h 32h 33h 34h 35h 36h 37h rstc 3fh ctmc0 ctmc1 ctmdl ctmdh ctmal ctmah dacr cmpc debc muxc psel opac opga bank 0 ~ bank 1 bank 1 40h speciap purpose data memory structure
rev. 1.11 20 april 11, 2017 rev. 1.11 21 april 11, 2017 HT45F56 shock detector flash mcu HT45F56 shock detector flash mcu special function register description most of the special function register details will be described in the relevant functional section. however, several registers require a separate description in this section. indirect addressing registers C iar0, iar1 the indirect addressing registers, iar0 and iar1, although having their locations in normal ram register space, do not actually physically exist as normal registers. the method of indirect addressing for ram data manipulation uses these indirect addressing registers and memory pointers, in contrast to direct memory addressing, where the actual memory address is specified. actions on the iar0 and iar1 registers will result in no actual read or write operation to these registers but rather to the memory loc ation specified by the ir corresponding memory pointers, mp0 or mp1. acting as a pair , iar0 and mp0 can together access data only from bank 0 while the iar1 register together with mp1 register can acce ss data from any data memory bank. as the indirect addressing registers are not physically implemented, reading the indirect addressing registers indirectly will return a result of 00h and writing to the registers indirectly will result in no operation. memory pointers C mp0, mp1 the indirect addressing registers, iar0 and iar1, although having their locations in normal ram register space, do not actually physically exist as normal registers. the method of indirect addressing for ram data manipulation uses these indirect addressing registers and memory pointers, in contrast to direct memory addressing, where the actual memory address is specifed. actions on the iar0 and iar1 registers will result in no actual read or write operatio n to these registers but rather to the memory location specifed by their corresponding memory pointers, mp0 or mp1. acting as a pair, iar0 and mp0 can together access data from bank 0 while the iar1 and mp1 register pair can access data from any bank. as the indirect addressing registers are not physically implemented, reading the indirect addressing registers indirectly will return a result of 00h and writing to the registers indirectly will result in no operation. indirect addressing program example example 1 data .section data adres1 db ? adres2 db ? adres3 db ? adres4 db ? block db ? code .section at 0 code org 00h start: mov a,04h ; setup size of block mov block,a mov a,offset adres1 ; accumulator loaded with frst ram address mov mp0,a ; setup memory pointer with frst ram address loop: clr iar0 ; clear the data at address defned by mp0 inc mp0 ; increment memory pointer sdz block ; check if last memory location has been cleared jmp loop continue: : the important point to note here is that in the example shown above, no reference is made to specifc ram addresses.
rev. 1.11 20 april 11, 2017 rev. 1.11 21 april 11, 2017 HT45F56 shock detector flash mcu HT45F56 shock detector flash mcu bank pointer C bp the data memory is divided into two banks, bank 0 and bank 1. selecting the required data memory area is achieved using the bank pointer , bp . the bank pointer bit 0 is used to select data memory bank 0 or bank 1. the data memory initialised to bank 0 after a reset except for a wdt tome-out reset in the power down mode in which case the data memory bank remains unaf fected. it should be noted that the special function data memory is not af fected by the bank selection, which means that the special function registers can be accessed irrespective of the value of the bank pointer . accessing data from bank 1 must be implemented using the indirect addressing. bp register bit 7 6 5 4 3 2 1 0 name dmbp0 r/w r/w por 0 bit 7~1 unimplemented, read as 0 bit 0 dmbp0 : data memory bank point bit 0 0: bank 0 1: bank 1 accumulator C acc the a ccumulator is central to the operation of any microcontroller and is clos ely related w ith operations carried out by the alu. the accumulator is the place where all intermediate results from the alu are stored. w ithout the accumulator it would be necessary to write the result of each c alculation or l ogical ope ration suc h a s a ddition, subt raction, shi ft, e tc., t o t he da ta me mory resulting i n highe r program ming and t iming overheads. da ta t ransfer operat ions usual ly i nvolve the t emporary st orage func tion of t he ac cumulator; for e xample, wh en t ransferring da ta be tween one user -defined register and another , it is necessary to do this by passing the data through the accumulator as no direct transfer between two registers is permitted. program counter low register C pcl to provide additional program control functions, the low byte of the program counter is made accessible to programmers by locating it within the special purpose area of the data memory . by manipulating this register , direct jumps to other program locations are easily implemented. loading a value directly into this pcl register will cause a jump to the specifed program memory location, however, as the register is only 8-bit wide, only jumps within the current program memory page are permitted. when such operations are used, note that a dummy cycle will be inserted. look-up table registers C tblp, tblh these three special function registers are used to cont rol operation of the look-up table which is stored in the program memory . tblp is the table pointer and indicates the location where the table data is located. their value must be setup before any table read commands are executed. their value can b e c hanged, f or e xample u sing t he inc o r dec i nstructions, a llowing f or e asy t able d ata pointing and reading. tblh is the location where the high order byte of the table data is stored after a table read data instruction has been executed. note that the lower order table data byte is transferred to a user defned location.
rev. 1.11 22 april 11, 2017 rev. 1.11 23 april 11, 2017 HT45F56 shock detector flash mcu HT45F56 shock detector flash mcu status register C status this 8-bit register contains the zero fag (z), carry fag (c), auxiliary carry fag (ac), overfow fag (ov), power down fag (pdf), and watchdog time-out fag (t o). these arithmetic/logical operation and system management fags are used to record the status and operation of the microcontroller. with the exceptio n of the t o and pdf fags, bits in the status register can be altered by instructions like most other registers. any data written into the status register will not change the t o or pdf fag. in addition, operations related to the status register may give dif ferent results due to the dif ferent instruction operati ons. the t o fag can be af fected only by a system power -up, a wdt time-out or by executing the clr wdt or hal t instruction. the pdf fag is af fected only by executing the halt or clr wdt instruction or during a system power-up. the z, ov, ac and c fags generally refect the status of the latest operations. ? c is set if an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation; otherwise c is cleared. c is also affected by a rotate through carry instruction. ? ac is set if an operation results in a carry out of the low nibbles in addition, or no borrow from the high nibble into the low nibble in subtraction; otherwise ac is cleared. ? z is set if the result of an arithmetic or logical operation is zero; otherwise z is cleared. ? ov is set if an operation results in a carry into the highest-order bit but not a carry out of the highest-order bit, or vice versa; otherwise ov is cleared. ? pdf is cleared by a system power-up or executing the clr wdt instruction. pdf is set by executing the halt instruction. ? to is cleared by a system power-up or executing the clr wdt or halt instruction. t o is set by a wdt time-out. in additio n, on entering an interrup t sequence or executing a subroutine call, the status register will not be pushed onto the stack automatically . if the contents of the status registers are important and if the subroutine can corrupt the status register, precautions must be taken to correctly save it.
rev. 1.11 22 april 11, 2017 rev. 1.11 23 april 11, 2017 HT45F56 shock detector flash mcu HT45F56 shock detector flash mcu status register bit 7 6 5 4 3 2 1 0 name to pdf ov z ac c r/w r r r/w r/w r/w r/w por 0 0 x x x x x: unknown bit 7~6 unimplemented, read as 0 bit 5 to : w atchdog t ime-out fag 0: after power up ow executing the clr wdt or halt instruction 1: a watchdog time-out occurred bit 4 pdf : power down fag 0: after power up ow executing the clr wdt instruction 1: by executing the halt instructin bit 3 ov : overfow fag 0: no overfow 1: an operation results in a carry into the highest-order bit but not a carry out of the highest-order bit or vice versa bit 2 z : zero fag 0: the result of an arithmetic or logical operation is not zero 1: the result of an arithmetic or logical operation is zero bit 1 ac : auxiliary fag 0: no auxiliary carry 1: an operation results in a carry out of the low nibbles, in addition, or no borrow from the high nibble into the low nibble in substraction bit 0 c : carry fag 0: no carry-out 1: an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation the c fag is also affected by a rotate through carry instruction.
rev. 1.11 24 april 11, 2017 rev. 1.11 25 april 11, 2017 HT45F56 shock detector flash mcu HT45F56 shock detector flash mcu eeprom data memory these d evices c ontain a n a rea o f i nternal e eprom da ta me mory. e eprom, wh ich st ands f or electrically e rasable progra mmable re ad onl y me mory, i s by i ts na ture a non-vol atile form of re-programmable memory , with data retention even when its power supply is removed. by incorporating this kind of data memory , a w hole new hos t of application pos sibilities are made available to the designer . the avail ability of eeprom storage allows information such as product identification numbers, calibration values, specific user data, system setup data or other product information to be stored directly within the product microcontroller . the process of reading and writing data to the eeprom memory has been reduced to a very trivial affair. capacity address 32 x 8 00h ~ 1fh eeprom data memory structure the eeprom data memory capacity is 328 bits for the device. unlike the program memory and ram data memory , the eeprom data memory is not directly mapped into memory space and is therefore not directly addressable in the same way as the other types of memory . read and write operations to the eeprom are carried out in single byte operations using an address and data register in bank 0 and a single control register in bank 1. eeprom registers three registers control the overall operation of the internal eeprom data memory . these are the address register , eea, the data register , eed and a single control register , eec. as both the eea and eed registers are located in sector 0, they can be directly accessed in the same was as any other special function register . the eec register , however , being located in sector 1, can be read from or written to indirectly using the mp1 memory pointer and indirect address ing regis ter, iar1. because the eec control register is located at address 40h in bank 1, the memory pointer low byte register, mp1, must frst be set to the value 40h and the bank pointer register , bp , set to the value, 01h, before any operations on the eec register are executed. register name bit 7 6 5 4 3 2 1 0 eea eea4 eea3 eea2 eea1 eea0 eed d7 d6 d5 d4 d3 d2 d1 d0 eec wren wr rden rd eeprom registers list eea register bit 7 6 5 4 3 2 1 0 name eea4 eea3 eea2 eea1 eea0 r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 bit 7~5 unimplemented, read as 0. bit 4~0 eea4~eea0 : data eeprom address bit 4 ~ bit0
rev. 1.11 24 april 11, 2017 rev. 1.11 25 april 11, 2017 HT45F56 shock detector flash mcu HT45F56 shock detector flash mcu eed register bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 d7~d0 : data eeprom data bit 7~bit0 eec register bit 7 6 5 4 3 2 1 0 name wren wr rden rd r/w r/w r/w r/w r/w por 0 0 0 0 bit 7~4 unimplemented, read as 0. bit 3 wren : data eeprom write enable 0: disable 1: enable this is the d ata eep rom w rite enable bit w hich mus t be s et high before d ata eeprom write operations are carried out. clearing this bit to zero will inhibit data eeprom write operations. bit 2 wr : eeprom write control 0: w rite cycle has fnished 1: activate a write cycle this i s t he da ta e eprom w rite c ontrol b it a nd wh en se t h igh b y t he a pplication program will activ ate a write cycle. this bit will be automatically reset to zero by the hardware after the write cycle has fnished. setting this bit high will have no ef fect if the wren has not frst been set high. bit 1 rden : data eeprom read enable 0: disable 1: enable this is the data eeprom read enable bit which must be set high before data eeprom read operations are carried out. clearing this bit to zero w ill inhibit d ata eeprom read operations. bit 0 rd : eeprom read control 0: read cycle has fnished 1: activate a read cycle this is the data eeprom read control bit and when set high by the applic ation program will activ ate a read cycle. this bit will be automatically reset to zero by the hardware after the read cycle has fnished. setting this bit high will have no ef fect if the rden has not frst been set high. note: the wren, wr, rden and rd can not be set to 1 at the same time in one instruction. the wr and rd can not be set to 1 at the same time.
rev. 1.11 26 april 11, 2017 rev. 1.11 27 april 11, 2017 HT45F56 shock detector flash mcu HT45F56 shock detector flash mcu reading data from the eeprom to read data from the eep rom, the read enable bit, rden , in the eec register must frs t be set high to enable the read function. the eeprom address of the data to be read must then be placed in the eea register . if the rd bit in the eec register is now set high, a read cycle will be initiated. setting the rd bit high will not initiate a read operation if the rden bit has not been set. when the read cycle term inates, the rd bit will be automatically cleared to zero, after which the data can be read from the eed register . the data will remain in the eed register until another read or write operation i s e xecuted. t he a pplication pr ogram c an po ll t he rd bi t t o de termine whe n t he da ta i s valid for reading. writing data to the eeprom to write data to the eeprom, the eeprom address of the data to be written must frst be placed in t he ee a regist er and t he dat a pla ced in t he ee d regist er. then t he writ e enabl e bit , wren, in the eec register must first be set high to enable the write function. after this, the wr bit in the e ec r egister m ust be i mmediately se t hi gh t o i nitiate a wri te c ycle. t hese t wo i nstructions must be executed consecutively . the global interrupt bit emi should also first be cleared before implementing any write operations, and then set again after the write cycle has started. note that setting the wr bit high will not initiate a write cycle if the wren bit has not been set. as the eeprom write cycle is controlled using an internal timer whose operation is asynchronous to microcontroller system clock, a certain time will elapse before the data will have been written into the eeprom. detecting when the write cycle has fnished can be implemented either by polling the wr bit in the eec register or by using the eeprom interrupt. when the write cycle terminates, the wr bit will be automatically cleared to zero by the microcontroller , informing the user that the data has been written to the eeprom. the application program can therefore poll the wr bit to determine when the write cycle has ended. write protection protection against inadvertent write operation is provided in several ways. after the device is powered on, the w rite enable bit in the control regis ter w ill be cleared preventing any w rite operations. also at power -on the bank pointer register , bp , will be reset to zero, which means that data memory bank 0 will be selec ted. as the eeprom control register is located in bank 1, this adds a f urther m easure o f p rotection a gainst sp urious wr ite o perations. du ring n ormal p rogram operation, ensuring that the w rite enable bit in the control register is cleared will safeguard against incorrect write operations. eeprom interrupt the eeprom write interrupt is generated when an eeprom write cycle has ended. the eeprom interrupt must first be enabled by setting the dee bit in the relevant interrupt register . when an eeprom write cycle ends, the def request fag will be set. if the global, eeprom interrupts are enabled and the stack is not full, a subroutine call to the eeprom interrupt vector will take place. when the interrupt is serviced, the eeprom interrupt fag def will be automatically cleared. the emi bit will also be automatically cleared to disable other interrupts.
rev. 1.11 26 april 11, 2017 rev. 1.11 27 april 11, 2017 HT45F56 shock detector flash mcu HT45F56 shock detector flash mcu programming considerations care must be taken that data is not inadvertently written to the eeprom. protection can be periodic b y e nsuring t hat t he w rite e nable b it i s n ormally c leared t o z ero wh en n ot wr iting. al so the bank pointer could be normally cleared to zero as this would inhibit access to bank 1 where the eeprom control register exist. although certainly not necessary , consideration might be given in the application program to the checking of the validity of new write data by a simple read back process. when writing data the wr bit must be set high immediately after the wren bit has been set high, to ensure the write cycle executes correctly . the global interrupt bit emi should also be cleared before a write cycle is executed and then re-enabled after the write cycle starts. note that the devic e should not enter the idle or sleep mode until the eeprom read or write operation is totally complete. otherwise, the eeprom read or write operation will fail. programming example reading data from the eeprom C polling method mov a , eeprom_adres ; user defned address mov e ea, a mov a , 040h ; setup memory pointer mp1 mov m p1, a ; mp1 points to eec register mov a , 01h ; setup bank pointer bp mov b p, a set i ar1.1 ; set rden bit, enable read operations set i ar1.0 ; start read cycle - set rd bit back: sz i ar1.0 ; check for read cycle end jmp b ack clr i ar1 ; disable eeprom write clr bp mov a , eed ; move read data to register mov r ead_data, a writing data to the eeprom C polling method mov a , eeprom_adres ; user defned address mov e ea, a mov a , eeprom_data ; user defned data mov e ed, a mov a , 040h ; setup memory pointer mp1 mov m p1, a ; mp1l points to eec register mov a , 01h ; setup bank pointer bp mov b p, a clr e mi set i ar1.3 ; set wren bit, enable write operations set i ar1.2 ; start write cycle - set wr bit set e mi back: sz i ar1.2 ; check for write cycle end jmp b ack clr i ar1 ; disable eeprom write clr bp
rev. 1.11 28 april 11, 2017 rev. 1.11 29 april 11, 2017 HT45F56 shock detector flash mcu HT45F56 shock detector flash mcu oscillator various oscillator types offer the user a wide range of functions according to their various application requirements. the fexible features of the oscillator functions ensure that the best optimisation can be achieved in terms of speed and power saving. oscillator selections and operation are selected through a combination of application program and relevant control registers. oscillator overview in additio n to being the source of the main system clock the oscillators also provide clock sources for t he w atchdog t imer a nd t ime b ase i nterrupts. e xternal o scillators r equiring so me e xternal components as well as fully integrated internal oscillators, requiring no external components, are provided to form a wide ra nge of bot h fa st and slow system oscill ators. the higher freque ncy oscillator provides higher performance but carries w ith it the dis advantage of higher pow er requirements, w hile the oppos ite is of cours e true for the low er frequency os cillator. w ith the capability of dynamically switching between fast and slow system clock, the device has the fexibility to optim ize the performance/power ratio, a feature especially important in power sensitive portable applications. type name frequency internal high speed rc hirc 8 mhz internal low speed rc lirc 32 khz oscillator types 6vwhp&orfn&rjxudwlrv there are two methods of generating the system clock, one high speed oscillator and one low speed oscillator. t he h igh sp eed o scillator i s t he i nternal 8 mhz r c o scillator, hi rc. t he l ow sp eed oscillator is the internal 32 kh z rc os cillator, lirc. s electing w hether the low or high s peed oscillator is used as the system oscillator is implemented using the hlclk and cks2~cks0 bits in the smod register and as the system clock can be dynamically selected. note that two oscillator selections m ust be m ade na mely one hi gh spe ed a nd one l ow spe ed syst em osc illators. it i s not possible to choose a no-oscillator selection for either the high or low speed oscillator. prescaler high speed oscillation low speed oscillation f h /2 f h /16 f h /64 f h /8 f h /4 f h /32 hlclk, cks2~cks0 f sys f sub f sub lirc f lirc hirc f h 6vwhp&orfn&rjxudwlrv
rev. 1.11 28 april 11, 2017 rev. 1.11 29 april 11, 2017 HT45F56 shock detector flash mcu HT45F56 shock detector flash mcu internal high speed rc oscillator C hirc the internal rc oscillator is a fully integrated system oscillator requiring no external components. the internal rc oscillator has a fixed frequency of 8 mhz. device trimming during the manufacturing process and the inclusion of internal frequency compensati on circuits are used to ensure that the infuence of the power supply voltage, temperature and process variations on the oscillation frequency are minimised. as a result, at a power supply of 5v and at a temperature of 25c degrees, the fxed oscillation frequency of 8mhz will have a tolerance within 2%. internal 32khz oscillator C lirc the internal 32 khz system oscillator is the low frequency oscillator choices and fully integrated with a typical frequency of 32 khz at 5v , requiring no external components for its implementation. device t rimming duri ng t he m anufacturing proc ess a nd t he i nclusion of i nternal fre quency compensation circ uits are used to ensure that the infuence of the power supply voltage, temperature and process variations on the oscillation frequency are minimised. supplementary oscillators the low speed oscillator , in addition to providing a system clock source is also used to provide a c lock so urce t o t wo o ther d evice f unctions. t hese a re t he w atchdog t imer a nd t he t ime b ase interrupts. operating modes and system clocks present day appl ications require that their mi crocontrollers have high performance but often sti ll demand that they consume as little power as possible, conficting requirements that are especially true i n ba ttery powe red por table a pplications. t he fa st c locks re quired for hi gh pe rformance wi ll by t heir na ture i ncrease c urrent c onsumption a nd of c ourse vi ce-versa, l ower spe ed c locks re duce current consumption. as holtek has provided thes e devices with both high and low speed clock sources and the means to switch between them dynamically , the user can optimise the operation of their microcontroller to achieve the best performance/power ratio. system clocks the device has dif ferent clock sources for both the cpu and peripheral function operation. by providing the user with a wide range of clock selections using register programming, a clock system can be confgured to obtain maximum application performance. the main system clock can come from either a high frequency f h or low frequency f sub source and is selected using the hlclk and cks2~cks0 bits in the smod register . the high speed system clock is sourced from the hirc oscillator while the low speed system clock source is sourced from the internal clock f sub . the other choice, which is a divided version of the high speed system oscillator has a range of f h /2~f h /64. there is one additional internal cloc k for the peripheral circuits, the t ime base clock, f tbc . the f tbc clock is sourced from the lirc oscillator and used as a source for the t ime base interrupt functions and for the tm.
rev. 1.11 30 april 11, 2017 rev. 1.11 31 april 11, 2017 HT45F56 shock detector flash mcu HT45F56 shock detector flash mcu prescaler high speed oscillation low speed oscillation f h /2 f h /16 f h /64 f h /8 f h /4 f h /32 hlclk, cks2~cks0 f sys f sub f sub lirc f lirc hirc f h wdt idlen f tbc f sys /4 tbck time base 0 time base 1 device clock confgurations ote hen the system clock source sys i sub iu i s d d ss uy su uiu u i ~f u iu susud u system operation modes 7huh duh vl[ gli ihuhw prghv ri rshudwlr iru wh plfurfrwuroohu hdf rh zlw lwv rz vshfldo fdudfwhulvwlfv dg zlf fd eh frvh dffruglj wr wh vshflilf shuirupdfh dg srzhu uhtxluhphwv ri wh dsso lfdwlr 7huh duh wzr prghv doo rzlj rupdo rshudwl r ri wh plfurfrwuroohu w h 1250/ 0rgh d g 6/ 2 0rgh 7 h uh pdllj irxu p rghv w h 6/ ((3 63((/ ,/( dg ,/( 0rghv duh xvhg zh wh plfurfrwuroohu &38 lv vzlwfhg ri i wr frvhuyh srzhu operation mode cpu f sys f sub f tbc normal on f h ~f h /64 on on slow on f sub on on idle0 off off on on idle1 off on on on sleep0 off off off off sleep1 off off on off normal mode v wh dph vxjjhvwv wlv lv rh ri wh pdl rshudwlj prghv zhuh wh plfurfrwuroohu dv doo ri lwv ixfwlrv rshudwlrdo dg zhuh wh vvwhp forfn lv surylghg e wh lj vshhg rvfloodwruv 7lv prgh rshudwhv door zlj wh plfurfr wuroohu wr rshudwh rupdoo zlw d forfn vrxufh zloo frph iurp wh lj vshhg rvfloodwruv ,5& 7h lj vshhg rvfloodwru zloo rzhyhu uvw eh glylghg e d udwlr udjlj iurp wr wh dfwxdo udwlr ehlj vhohfwhg e wh &.6a&.6 dg /&/. elwv l wh 602 uhjlvwhu owrxj d lj vshhg rv floodwru lv xv hg uxlj wh plfurfrwuroohu dw d glylghg forfn udwlr uhgxfhv wh rshudwlj fxuuhw
rev. 1.11 30 april 11, 2017 rev. 1.11 31 april 11, 2017 HT45F56 shock detector flash mcu HT45F56 shock detector flash mcu slow mode this is also a mode where the microcontroller operates normally altho ugh now with a slower speed clock sou rce. t he c lock sou rce u sed wi ll b e fr om f sub . t he f sub c lock i s d erived fr om t he l irc oscillator. running the microcontroller in this mode allows it to run with much lower operating currents. in the slow mode, the f h is switched off . sleep0 mode the sl eep0 mo de i s e ntered wh en a n hal t i nstruction i s e xecuted a nd wh en t he i dlen b it i s low. in the sleep0 mode the cpu will be stopped and the f sub clock will also be stopped as the watchdog t imer function is disabled. sleep1 mode the sl eep1 mo de i s e ntered wh en a n hal t i nstruction i s e xecuted a nd wh en t he i dlen b it i s low. in the sleep1 mode the cpu will be stopped. however , the f sub clock will continue to run as the w atchdog t imer function is enabled. idle0 mode the idle0 mode is entered when an hal t instruction is executed and when the idlen bit is high and the fsyson bit is low . in the idle0 mode the system oscillator will be inhibited from driving the c pu b ut so me p eripheral f unctions wi ll r emain o perational su ch a s t he w atchdot t imer a nd tms. in the idle0 mode, the system oscillator will be stopped. idle1 mode the idle1 mode is entered when an hal t instruction is executed and when the idlen bit is high and the fsyson bit is high. in the idle1 mode the system oscillator will be inhibited from driving the cpu but may contimue to provide a clock source to keep some peripheral functions operational such as the w atchdot t imer and tms. in the idle1 mode, the system oscillator wil l continue to run and this system oscillator mayt be high or low speed system oscillator . in ield1 mode, the watchdog t imer clock, f sub , will be switched on. control registers the register, smod, is used for overall control of the internal clocks within the device . smod register bit 7 6 5 4 3 2 1 0 name cks2 cks1 cks0 lto hto idlen hlclk r/w r/w r/w r/w r r r/w r/w por 0 0 0 0 0 1 1 bit 7~5 : system clock selection 000: f sub 001: f sub 010: f h /64 011: f h /32 100: f h /16 101: f h /8 110: f h /4 111: f h /2 these three bits are used to select which clock is used as the system clock source. in addition to the system clock source, which can be the f sub clock source, a divided version of the high speed system oscillator can also be chosen as the system clock source.
rev. 1.11 32 april 11, 2017 rev. 1.11 33 april 11, 2017 HT45F56 shock detector flash mcu HT45F56 shock detector flash mcu bit 4 unimplemented, read as 0. bit 3 lto : low speed system oscillator ready fag 0: not ready 1: ready this is the low speed system oscilla tor ready fag which indicates when the low speed system oscillator is stable after pow er on reset or a wake-up has occurred. the fag will be low when in the sleep0 mode, but after a wake-up has occurred the fag will change to a high level after 1~2 cycles as the lirc oscillator is used. bit 2 hto : high speed system oscillator ready fag 0: not ready 1: ready this is the high speed system oscillator ready fag which indicates when the high speed system oscillator is stable. this fag is cleared to 0 by hardware when the device is powered on and then changes to a high level after the high speed system oscillator is stable. therefore this fag will always be read as 1 by the application program after device power-on. bit 1 idlen : idle mode control 0: disable 1: enable this is the idle mode control bit and determines what happens when the ha lt instruction is executed. if this bit is high, when a hal t instruction is executed the device will enter the idle mode. in the idle1 mode, the cpu will stop running but the system clock will continue to keep the peripheral functions operational, as the fsyson bit is high. if the fsyson bit is low , the cpu and the system clock will all stop in the idle0 mode. if this bit is low , the device will enter the sleep mode when a halt instruction is executed. bit 0 hlclk : system clock selection 0: f h /2 ~ f h /64 or f sub 1: f h this bit is used to select if the f h clock, the f h /2 ~ f h /64 clock or the f sub clock is used as the system clock. when this bit is high, the f h clock will be selected and if low the f h /2 ~ f h /64 or f sub clock will be selected. when the system clock switches from the f h clock to the f sub clock and the f h clock will be automatically switched of f to conserve power. name fsyson rstf lvrf wrf r/w r/w r/w r/w r/w por 0 0 x 0 x: unknown bit 7 fsyson : f sys control in idle mode 0: disable 1: enable bit 6~4 unimplemented, read as 0. bit 3 rstf : reset control register software reset fag described elsewhere. bit 2 lvrf : lvr function reset fag described elsewhere. bit 1 unimplemented, read as 0. bit 0 wrf : wdt control register software reset fag described elsewhere.
rev. 1.11 32 april 11, 2017 rev. 1.11 33 april 11, 2017 HT45F56 shock detector flash mcu HT45F56 shock detector flash mcu operating mode switching the d evices c an swi tch b etween o perating m odes d ynamically a llowing t he u ser t o se lect t he b est performance/power ratio for the pres ent task in hand. in this w ay microcontroller operations that do not require high performance can be executed using slower clocks thus requiring less operating current and prolonging battery life in portable applications. in simple terms, mode switching between the normal mode and slow mode is executed using the hlclk bit and cks2~cks0 bits in the smod register while mode switching from the normal/ slow modes to the sleep/ idle modes is executed via the hal t instruction. when a hal t instruction is executed, whether the device enters the idle mode or the sleep mode is determined by the condition of the idlen bit in the smod register and fsyson in the smod1 register . when the hlclk bit switches to a low level, which implies that clock source is switched from the high speed clock source, fh, to the clock source, f h /2~ f h /64 or f sub . if the clock is from the f sub , the high speed clock source will stop running to conserve power . when this happens it must be noted that the f h /16 and f h /64 internal clock sources will also stop running, which may af fect the operation of other internal functions such as the tms. normal f sys =f h ~f h /64 f h on cpu run f sys on f sub on slow f sys =f sub f sub on cpu run f sys on f h off idle0 halt instruction executed cpu stop idlen=1 fsyson=0 f sys off f sub on idle1 halt instruction executed cpu stop idlen=1 fsyson=1 f sys on f sub on sleep1 halt instruction executed f sys off cpu stop idlen=0 f sub on wdt on sleep0 halt instruction executed f sys off cpu stop idlen=0 f sub off wdt off
rev. 1.11 34 april 11, 2017 rev. 1.11 35 april 11, 2017 HT45F56 shock detector flash mcu HT45F56 shock detector flash mcu normal mode to slow mode switching when r unning i n t he nor mal mo de, wh ich u ses t he h igh sp eed sy stem o scillator, a nd t herefore consumes m ore powe r, t he syst em c lock c an swi tch t o run i n t he sl ow mode by se tting t he hlclk bit to 0 and setting the cks2~cks0 bits to 000 or 001 in the smod register . this will then use the low speed system oscillator which will consume less power . users may decide to do this for certain operations which do not require high performance and can subsequently reduce power consumption. the slow mode is sourced from the lirc oscillator and therefore requires this oscillator to be stable before full mode switching occurs. this is monitored using the lto bit in the smod register. normal mode slow mode cks2~cks0 = 00xb & hlclk = 0 sleep0 mode idlen=0, wdt is off, halt instruction is executed idle0 mode idlen=1, fsyson=0 halt instruction is executed idle1 mode halt instruction is executed idlen=0, wdt is on, halt instruction is executed sleep1 mode idlen=1, fsyson=1
rev. 1.11 34 april 11, 2017 rev. 1.11 35 april 11, 2017 HT45F56 shock detector flash mcu HT45F56 shock detector flash mcu slow mode to normal mode switching in slow mode the system clock is derived from f sub . t o switch back to the normal mode, where the high speed system oscilla tor is used, the hlclk bit should be set to 1 or hlclk bit is 0 but the cks2~cks0 feld is set to 01x or 1xx. as a certain amount of time will be required for the high frequency clock to stablise, the status of the hto bit is checked. normal mode slow mode or hlclk=1 sleep0 mode idlen=0, wdt off halt instruction is executed sleep1 mode idle0 mode idle1 mode cks2~cks0 00x as hlclk=0 idlen=0, wdt on halt instruction is executed idlen=1, fsyson=0 halt instruction is executed idlen=1, fsyson=1 halt instruction is executed entering the sleep0 mode there is only one way for the devic e to enter the sleep0 mode and that is to execute the hal t instruction in the application program with the idlen bit in the smod register equal to 0 and the wdt is of f. when this instruction is executed under the conditions described above, the following will occur: ? the system clock, wdt clock and t ime base clock will be stopped and the application program will stop at the "halt" instruction. ? the data memory contents and registers will maintain their present condition. ? the i/o ports will maintain their present conditions. ? in the status register, the power down fag pdf will be set, and wdt timeout fag t o will be cleared. ? the wdt will be cleared and stopped as the wdt is disabled.
rev. 1.11 36 april 11, 2017 rev. 1.11 37 april 11, 2017 HT45F56 shock detector flash mcu HT45F56 shock detector flash mcu entering the sleep1 mode there is only one way for the devic e to enter the sleep1 mode and that is to execute the hal t instruction in the application program with the idlen bit in the smod register equal to 0 and the wdt is on. when this instruction is executed under the conditions described above, the following will occur: ? the system clock and t ime base clock will be stopped and the application program will stop at the "halt" instruction. however, the wdt clock will continue to run. ? the data memory contents and registers will maintain their present condition. ? the i/o ports will maintain their present conditions. ? in the status register, the power down fag pdf will be set, and wdt timeout fag t o will be cleared. ? the wdt will be cleared and resume counting as the wdt is enabled. entering the idle0 mode there is only one way for the device to enter the idle0 mode and that is to execute the hal t instruction in the application program with the idlen bit in the smode register equal to 1 and the fsyson bit in the smod1 regi ster equal to 0. when this instruction is executed under the conditions described above, the following will occur: ? the system clock will be stopped and the application program will stop at the halt instruction, but the t ime base clock will be on. ? the data memory contents and registers will maintain their present condition. ? the i/o ports will maintain their present conditions. ? in the status register, the power down fag pdf will be set, and wdt timeout fag t o will be cleared. ? the wdt will be cleared and resume counting if the wdt function is enabled. entering the idle1 mode there is only one way for the device to enter the idle1 mode and that is to execute the hal t instruction in the application program with idlen bit in the smode register equal to 1 and the fsyson bit in the smod1 regi ster equal to 1. when this instruction is executed under the conditions described above, the following will occur: ? the system clock and t ime base clock will be on but the application program will stop at the halt instruction. ? the data memory contents and registers will maintain their present condition. ? the i/o ports will maintain their present conditions. ? in the status register, the power down fag pdf will be set, and wdt timeout fag t o will be cleared. ? the wdt will be cleared and resume counting if the wdt function is enabled.
rev. 1.11 36 april 11, 2017 rev. 1.11 37 april 11, 2017 HT45F56 shock detector flash mcu HT45F56 shock detector flash mcu standby current considerations as the main reason for entering the sleep or idle mode is to keep the current consumption of the device to as low a value as possible, perhaps only in the order of several micro-amps except in the idle1 mode , t here a re ot her c onsiderations whi ch m ust a lso be t aken i nto a ccount by t he c ircuit designer if the power consumption is to be minimised. special attention must be made to the i/o pins on the device. all high-impedance input pins must be connected to either a fxed high or low level as any foating input pins could create internal oscillations and result in increased current consumption. this also applies to devices which have dif ferent package types, as there may be unbonbed pins. these must either be setup as outputs or if setup as inputs must have pull-high resistors connected. care must also be taken with the loads, which are connected to i/o pins, which are setup as outputs. these should be placed in a condition in which minimum current is drawn or connected only to external circuits that do not draw current, such as other cmos inputs. in the idle1 mode the systen oscillator is on, if the peripheral function clock source is derived from the high speed system oscillator, the additional standby current will also be perhaps in the order of several hundred micro- amps. wake-up to minimise power consumption the device can enter the sleep or any idle mode, where the cpu will be switched of f. however , when the device is woken up again, it will take a considerable time for the original system oscillator to restart, stablise and allow normal operation to resume. after the system enters the sleep or idle mode, it can be woken up from one of various sources listed as follows: ? an external reset ? an external falling edge on port a ? a system interrupt ? a wdt overfow if the system is woken up by an external reset, the device will experience a full system reset. however, if the device is woken up by a wdt overfow , a w atchdog t imer reset will be initiated. although both of these wake-up methods will initiate a reset operation, the actual source of the wake-up can be determined by examining the t o and pdf flags. the pdf flag is cleared by a system power -up or executing the clear w atchdog t imer instructions and is set when executing the halt instruction. the t o fag is set if a wdt time-out occurs, and causes a wake-up that only resets the program counter and stack pointer, the other fags remain in their original status. each pin on port a can be setup using the p awu register to permit a negative transition on the pin to wake up the system . when a port a pin wake-up occurs, the program wil l resume executi on at the i nstruction f ollowing t he halt i nstruction. i f t he sy stem i s wo ken u p by a n i nterrupt, t hen two possible situations may occur . the frst is where the related interrupt is disabled or the interrupt is enabled but the stack is full, in which case the program will resume execution at the instruction following the hal t instruction. in this situation, the interrupt which woke up the device will not be immediately serviced, but will rather be serviced later when the related interrupt is fnally enabled or when a stack level becomes free. the other situation is where the related interrupt is enabled and the stack is not full, in which case the regular interrupt response takes place. if an interrupt request flag i s se t hi gh be fore e ntering t he sle ep or idl e mode, t he wa ke-up func tion of t he re lated interrupt will be disabled.
rev. 1.11 38 april 11, 2017 rev. 1.11 39 april 11, 2017 HT45F56 shock detector flash mcu HT45F56 shock detector flash mcu watchdog timer the w atchdog t imer is provided to prevent program malfunctions or sequences from jumping to unknown locations, due to certain uncontrollable external events such as electrical noise. watchdog timer clock source the w atchdog t imer c lock sourc e i s provided by t he i nternal f sub c lock de rived from t he l irc oscillator. the lirc internal oscillator has an approximate frequency of 32 khz and this specifed internal clock period can vary with v dd , temperature and process variations. the w atchdog t imer source clock is then subdivided by a ratio of 2 8 to 2 15 to give longer timeouts, the actual value being chosen using the ws2~ws0 bits in the wdtc register. watchdog timer control register a single register , wdtc, controls the required timeout period as well as the enable/disable operation. this register controls the overall operation of the w atchdog t imer. the wrf software reset fag is used to indicate whether the wdt control register software reset occurs or not. wdtc register bit 7 6 5 4 3 2 1 0 name we4 we3 we2 we1 we0 ws2 ws1 ws0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 1 0 1 0 0 1 1 bit 7~3 : wdt function enable control 10101: disabled 01010: enabled other values: reset mcu if these bits are changed due to adverse environmental conditions, the microcontroller will be reset. the reset operation will be activated after 2~3 lirc clock cycles and the wrf bit in the smod1 register will be set to 1. bit 2~0 : wdt time-out period selection 000: 2 8 /f sub 001: 2 9 /f sub 010: 2 10 /f sub 011: 2 11 /f sub 100: 2 12 /f sub 101: 2 13 /f sub 110: 2 14 /f sub 111: 2 15 /f sub these t hree b its d etermine t he d ivision r atio o f t he wa tchdog t imer so urce c lock, which in turn determines the time-out period.
rev. 1.11 38 april 11, 2017 rev. 1.11 39 april 11, 2017 HT45F56 shock detector flash mcu HT45F56 shock detector flash mcu smod1 register bit 7 6 5 4 3 2 1 0 name fsyson rstf lvrf wrf r/w r/w r/w r/w r/w por 0 0 x 0 x: unknown bit 7 fsyson : f control in idle mode described elsewhere. bit 6~4 unimplemented, read as 0 bit 3 rstf : reset control register software reset fag described elsewhere. bit 2 lvrf : lvr function reset fag described elsewhere. bit 1 unimplemented, read as 0 bit 0 wrf : wdt control register software reset fag 0: not occurred 1: occurred this b it i s se t t o 1 b y t he w dt c ontrol r egister so ftware r eset a nd c leared b y t he application program. note that this bit can only be cleared to 0 by the application program. watchdog timer operation the w atchdog t imer ope rates by provi ding a de vice re set whe n i ts t imer ove rfows. t his m eans that i n t he a pplication pro gram a nd dur ing nor mal ope ration t he use r ha s t o st rategically c lear t he watchdog t imer before it overfows to prevent the w atchdog t imer from executing a reset. this is done using the clear watchdog instruction. if the program malfunctions for whatever reason, jumps to an unknown location, or enters an endless loop, the clear instructio n will not be executed in the correct manner, in which case the w atchdog t imer will overfow and reset the device. w ith regard to the w atchdog t imer enable/disable function, there are fve bits, we4~we0, in the wdtc register to of fer the enable /disable control and reset control of the w atchdog t imer. the wdt function will be disa bled when the we 4~we0 bit s are set to a val ue of 10101b whil e the wdt funct ion wi ll be enabled if the we4~we0 bits are equal to 01010b. if the we4~we0 bits are set to any other values, other than 01010b and 10101b, it will reset the device after 2~3 f lirc clock cycles. after power on these bits will have a value of 01010b. we4 ~ we0 bits wdt function 10101b disable 01010b enable any other value reset mcu watchdog timer enable/disable control under norm al progra m ope ration, a w atchdog t imer t ime-out wi ll i nitialise a de vice re set a nd se t the status bit t o. however , if the system is in the sleep or idle mode, when a w atchdog t imer time-out occurs, the t o bit in the status register will be set and only the program counter and stack pointer will be reset. four methods can be adopted to clear the contents of the w atchdog t imer. the frst is a wdt reset, which means a certain value except 01010b and 10101b written into the we4~we0 feld, the second is using the w atchdog t imer software clea r instructi on, the third is using a halt instruction and the fourth is an external hardware reset. there is only one method of using software instruction to clear the w atchdog t imer. that is to use the single clr wdt instruction to clear the wdt contents.
rev. 1.11 40 april 11, 2017 rev. 1.11 41 april 11, 2017 HT45F56 shock detector flash mcu HT45F56 shock detector flash mcu the maximum time out period is when the 2 15 division ratio is selected. as an example, with a 32 khz lirc oscillator as its source clock, this will give a maximum watchdog period of around 1 second for the 2 15 division ratio and a minimum timeout of 7.8ms for the 2 8 division ration. clr wdt instruction 8-stage divider wdt prescaler we4~we0 bits wdtc register reset mcu f sub f sub /2 8 8-to-1 mux clr ws2~ws0 (f sub /2 8 ~ f sub /2 15 ) wdt time-out (2 8 /f sub ~ 2 15 /f sub ) halt instruction res pin reset watchdog timer reset and initialisation a reset function is a fundamental part of any microcontroller ensuring that the devices can be set to some predetermined condition irrespective of outside parameters. the most important reset condition is after power is frst applied to the microcontroller . in this case, internal circuitry will ensure that the mi crocontroller, after a short del ay, will be in a well defined state and rea dy to execute t he fr st p rogram i nstruction. af ter t his p ower-on r eset, c ertain i mportant i nternal r egisters will be set to defned states before the program commences. one of these registers is the program counter, which will be reset to zero forcing the microcontroller to begin program execution from the lowest program memory address. in a ddition t o t he p ower-on r eset, si tuations m ay a rise wh ere i t i s n ecessary t o f orcefully a pply a reset condition when the microcontroller is running. one example of this is where after power has be en a pplied a nd t he m icrocontroller i s a lready ru nning, t he res l ine i s fo rcefully pu lled l ow. in such a case, known as a normal operation reset, some of the microcontroller registers remain unchanged allowing the microcontroller to proceed with normal operation after the reset line is allowed to return high. another type of reset is w hen the w atchdog t imer overflow s and resets the microcontroller . a ll types of reset operations result in different register conditions being setup. another reset exists in the form of a low v oltage reset, l vr, where a full reset is implemented in situations where the power supply voltage falls below a certain threshold. reset functions there are five w ays in w hich a microcontroller res et can occur , through events occurring both internally and externally.
rev. 1.11 40 april 11, 2017 rev. 1.11 41 april 11, 2017 HT45F56 shock detector flash mcu HT45F56 shock detector flash mcu power-on reset the most fundamental and unavoidable reset is the one that occurs afte r power is frst applied to the microcontroller. as well as ensuring that the program memory begins execution from the frst memory address, a power -on reset also ensures that certain other registers are preset to known conditions. all the i/o port and port control registers will power up in a high condition ensuring that all pins will be frst set to inputs. v dd power - on reset sst time -out t rstd 1rwh w 567' lv srzhur ghod zlwk wslfdo wlph pv power-on reset timing chart res pin reset although the microcontroller has an internal rc reset function, if the v dd power supply rise time is not fast enough or does not stabilise quickly at power -on, the internal reset function may be incapable of providing proper reset operation. for this reason it is recommended that an external rc network is connected to the res pin, whose additional time delay will ensure that the res pin remains low for an extended period to allow the power supply to stabilise. during this time delay , normal operation of the microcontroller will be inhibited. after the res line reaches a certain voltage value, the reset delay time t rstd is invoked to provide an extra delay time after which the microcontroller will begin normal operation. the abbreviation sst in the fgures stands for system start-up t imer. for most applicat ions a resistor connected between v dd and the res pin and a capacitor connected between vss and the res pin will provide a suitable external reset circuit. any wiring connected to t he res p in sho uld b e k ept a s sho rt a s p ossible t o m inimize a ny st ray n oise i nterference. fo r applications that operate within an environment where more noise is present the enhanced reset circuit shown is recommended. more information regarding external reset circuits is located in application note ha0075e on the holtek website. vdd v dd res 10 ko~ 100 ko 0. 01 f ** 1n 4148 * vss 0.1f~1f 300 o* 1rwh ,w lv uhfrpphghg wkdw wklv frpsrhw lv dgghg iru dgghg (6' surwhfwlr ,w lv uhfrpp hghg wkdw wklv frpsrhw lv dgghg l hylurphwv zkhuh srzhu olh rlvh lv vljlfdw external res circuit
rev. 1.11 42 april 11, 2017 rev. 1.11 43 april 11, 2017 HT45F56 shock detector flash mcu HT45F56 shock detector flash mcu pulling the res pin low using exter nal hardware will also execute a device reset. in this case, as in the case of other resets, the program counter will reset to zero and program execution initiated from this point. internal reset t rstd +t sst res 0.9v dd 0.4v dd 1rwh w 567' lv srzhur ghod zlwk wslfdo wlph pv res reset timing chart there is an intern al reset control register , rstc, which is used to provide a reset when the device operates abnormal ly due to the environmental noise interference. if the content of the rstc register is set to any value other than 01010101b or 10101010b, it will reset the device after 2~3 f lirc clock cycles. after power on the register will have a value of 01010101b. rstc7 ~ rstc0 bits reset function 01010101b i/o or other functions 10101010b res function any other value reset mcu reset function control ? rstc register bit 7 6 5 4 3 2 1 0 name rstc7 rstc6 rstc5 rstc4 rstc3 rstc2 rstc1 rstc0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 1 0 1 0 1 0 1 bit 7~0 rstc7~rstc0 : reset function control 01010101: i/o or other functions 10101010: res function other values: reset mcu if these bits are changed due to adverse environmental conditions, the microcontroller will b e r eset. t he r eset o peration wi ll b e a ctivated a fter 2 ~3 l irc c lock c ycles a nd the rstf bit in the smod1 register will be set to 1. all reset will reset this register as por value except the wdt time-out reset.
rev. 1.11 42 april 11, 2017 rev. 1.11 43 april 11, 2017 HT45F56 shock detector flash mcu HT45F56 shock detector flash mcu ? smod1 register bit 7 6 5 4 3 2 1 0 name fsyson rstf lvrf wrf r/w r/w r/w r/w r/w por 0 0 x 0 x: unknown bit 7 fsyson : f control in idle mode described elsewhere. bit 6~4 unimplemented, read as 0 bit 3 rstf : reset control register software reset fag 0: not occurred 1: occurred this bit is set to 1 by the rstc control register software reset and cleared by the application program. note that this bit can only be cleared to 0 by the application program. bit 2 lvrf : lvr function reset fag described elsewhere. bit 1 unimplemented, read as 0 bit 0 wrf : wdt control register software reset fag described elsewhere. low voltage reset C lvr the micr ocontroller contains a low voltage reset circuit in order to monitor the supply voltage of the device. the l vr function is always enabled with a specifc l vr voltag e, v lvr . if the supply voltage of the device drops to within a range of 0.9v~v lvr such as might occur when changing the battery , the l vr will automatically reset the device internally and the l vrf bit in the smod1 register will also be set to 1. for a valid l vr signal, a low supply voltage, i.e., a voltage in the range between 0.9v~ v lvr must exist for a time greater than that specifed by t lvr in the l vr characteristics. if the low supply voltage state does not exceed this value, the l vr will ignore the low supply voltage and will not perform a reset functio n. the actual v lvr value is 2.1v and the l vr circuit will reset the device when the supply voltage is less than 2.1v for more than the t lvr time. note that the l vr function will be automatically disabled when the device enters the power down mode. lvr internal reset t rstd + t sst 1rwh w 567' lv srzhur ghod zlwk wslfdo wlph pv low voltage reset timing chart
rev. 1.11 44 april 11, 2017 rev. 1.11 45 april 11, 2017 HT45F56 shock detector flash mcu HT45F56 shock detector flash mcu ? smod1 register bit 7 6 5 4 3 2 1 0 name fsyson rstf lvrf wrf r/w r/w r/w r/w r/w por 0 0 x 0 x: unknown bit 7 fsyson : f control in idle mode described elsewhere. bit 6~4 unimplemented, read as 0 bit 3 rstf : reset control register software reset fag described elsewhere. bit 2 lvrf : lvr function reset fag 0: not occurred 1: occurred this bit is set to 1 when a specifc low voltage reset condition occurs. note that this bit can only be cleared to 0 by the application program. bit 1 unimplemented, read as 0 bit 0 wrf : wdt control register software reset fag described elsewhere. watchdog time-out reset during normal operation the w atchdog time-out reset during normal operation is the same as the hardw are low v oltage reset except that the w atchdog time-out fag t o will be set to 1. wdt time -out internal reset t rstd + t sst 1rwh w 567' lv srzhur ghod zlwk wslfdo wlph pv wdt time-out reset during normal operation timing chart watchdog time-out reset during sleep or idle mode the w atchdog time-out reset during sleep or idle mode is a little dif ferent from other kinds of re set. mo st of t he c onditions re main unc hanged e xcept t hat t he pro gram count er a nd t he st ack pointer will be cle ared to 0 and the t o fag will be set to 1. refer to the a.c. characteristics for sst details. wdt time -out internal reset t sst wdt time-out reset during sleep or idle mode timing chart
rev. 1.11 44 april 11, 2017 rev. 1.11 45 april 11, 2017 HT45F56 shock detector flash mcu HT45F56 shock detector flash mcu reset initial conditions the dif ferent types of reset described af fect the reset fags in dif ferent ways. these fags, known as p df and t o are located in the s tatus regis ter and are controlled by various microcontroller operations, su ch a s t he sl eep o r i dle mo de f unction o r w atchdog t imer. t he r eset f lags a re shown in the table: to pdf reset function 0 0 power-on reset u u res lvr reset during normal or slow mode operation 1 u wdt time-out reset during normal or slow mode operation 1 1 wdt time-out reset during idle or sleep mode operation u stands for unchanged the following table indicates the way in which the various components of the microcontroller are affected after a power-on reset occurs. item reset function program counter reset to zero interrupts all interrupts will be disabled wdt, time base clear after reset, wdt begins counting timer modules timer modules will be turned off input/output ports i/o ports will be setup as inputs stack pointer stack pointer will point to the top of the stack the dif ferent kinds of resets all af fect the internal registers of the micr ocontroller in dif ferent ways. to ensure reliable continuation of normal program execution after a reset occurs, it is important to know what condition the microcontroller is in after a particular reset occurs. the following table describes how each type of reset affects the microcontroller internal registers.
rev. 1.11 46 april 11, 2017 rev. 1.11 47 april 11, 2017 HT45F56 shock detector flash mcu HT45F56 shock detector flash mcu register reset (power on) res reset (normal operation) lvr reset (normal operation) wdt time-out (normal operation) wdt time-out (idle or sleep)* iar0 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu mp0 1000 0000 1000 0000 1000 0000 1000 0000 1uuu uuuu iar1 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu mp1 1000 0000 1000 0000 1000 0000 1000 0000 1uuu uuuu bp ---- ---0 ---- ---0 ---- ---0 ---- ---0 ---- ---0 acc xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu pcl 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 tblp xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu tblh --xx xxxx --uu uuuu --uu uuuu --uu uuuu --uu uuuu status --00 xxxx --uu uuuu --uu uuuu --1u uuuu --11 uuuu smod 000- 0011 000- 0011 000- 0011 000- 0011 uuu- uuuu intc0 -000 0000 -000 0000 -000 0000 -000 0000 -uuu uuuu intc1 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 pa 111- -111 111- -111 111- -111 111- -111 uuu- -uuu pac 111- -111 111- -111 111- -111 111- -111 uuu- -uuu papu 000- -000 000- -000 000- -000 000- -000 uuu- -uuu pawu 000- -000 000- -000 000- -000 000- -000 uuu- -uuu wdtc 0101 0011 0101 0011 0101 0011 0101 0011 uuuu uuuu tbc 0011 -111 0011 -111 0011 -111 0011 -111 uuuu -uuu smod1 0--- 0x-0 0--- uu-u 0--- u1-u 0--- uu-u u--- uu-u eea ---0 0000 ---0 0000 ---0 0000 ---0 0000 ---u uuuu eed 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu rstc 0101 0101 0101 0101 0101 0101 0101 0101 uuuu uuuu ctmc0 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu ctmc1 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu ctmdl 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu ctmdh ---- --00 ---- --00 ---- --00 ---- --00 ---- --uu ctmal 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu ctmah ---- --00 ---- --00 ---- --00 ---- --00 ---- --uu eec ---- 0000 ---- 0000 ---- 0000 ---- 0000 ---- uuuu dacr 0-00 0000 0-00 0000 0-00 0000 0-00 0000 u-uu uuuu cmpc x-00 ---1 x-00 ---1 x-00 ---1 x-00 ---1 u-uu ---u debc ---- -000 ---- -000 ---- -000 ---- -000 ---- -uuu muxc --00 --00 --00 --00 --00 --00 --00 --00 --uu --uu psel --00 0111 --00 0111 --00 0111 --00 0111 --uu uuuu opac -1-- --00 -1-- --00 -1-- --00 -1-- --00 -u-- --uu opga ---- 1111 ---- 1111 ---- 1111 ---- 1111 ---- uuuu note: u stands for unchanged x stands for unknown - stands for unimplemented
rev. 1.11 46 april 11, 2017 rev. 1.11 47 april 11, 2017 HT45F56 shock detector flash mcu HT45F56 shock detector flash mcu input/output ports holtek m icrocontrollers of fer c onsiderable fe xibility on t heir i/ o port s. w ith t he i nput or out put designation of every pin fully under user program control, pull-high selections for all ports and wake-up selections on certain pins, the user is provided with an i/o structure to meet the needs of a wide range of application possibilities. the device providea bidirectional input/output lines labeled w ith port name p a . thes e i/o ports are mapped to the ram data memory with specific addresses as shown in the special purpose data memory table. a ll of thes e i/o ports can be used for input and output operations. for input operation, these ports are non-latch ing, which means the inputs must be ready at the t2 rising edge of instruction mov a, [m], where m denotes the port address. for output operation, all the data is latched and remains unchanged until the output latch is rewritten. register name bit 7 6 5 4 3 2 1 0 pa pa7 pa6 pa5 pa2 pa1 pa0 pac pac7 pac6 pac5 pac2 pac1 pac0 papu papu7 papu6 papu5 papu2 papu1 papu0 pawu pawu7 pawu6 pawu5 pawu2 pawu1 pawu0 i/o registers list : unimplemented, read as 0. : port a data bit 0: data 0 1: data 1 : port a pin type selection 0: output 1: input : port a pin pull-high function control 0: disable 1: enable : port a pin wake-up function control 0: disable 1: enable pull-high resistors many product applications require pull-high resistors for their switch inputs usually requiring the use of an external resistor . t o eliminate the need for these external resistors, all i/o pins, when confgured as an input have the capability of being connected to an internal pull-high resistor . these pull-high resistors are selected using the relevant pull-high control registers and are implemented using weak pmos transistors.
rev. 1.11 48 april 11, 2017 rev. 1.11 49 april 11, 2017 HT45F56 shock detector flash mcu HT45F56 shock detector flash mcu port a wake-up the hal t instruction forces the microcontroller into the sleep or idle mode which preserves power, a feature that is important for battery and other low-power applications. v arious methods exist to wake-up the microcontroller, one of which is to change the logic condition on one of the port a pins from high to low . this function is especially suitable for applications that can be woken up via extern al switches. each pin on port a can be selected individually to have this wake-up feature using the pawu register. i/o port control register each port has its own control register , known as p ac, which controls the input/output confguration. with this control register , each i/o pin with or without pull-high resistors can be reconfigured dynamically under software control. for the i/o pin to function as an input, the corresponding bit of the control registe r must be written as a 1. this will then allow the logic state of the input pin to be directly read by instructions. when the corresponding bit of the control register is written as a 0, the i/o pin will be setup as a cmos output. if the pin is currently setup as an output, instructions can still be used to read the output register. however, it should be noted that the program will in fact only read the status of the output data latch and not the actual logic status of the output pin. pin-shared functions the fexibility of the microcontroller range is greatly enhanced by the use of pins that have more than one function. limited numbers of pins can force serious design constraints on designers but by supplying pins with multi-functions , many of these diffculties can be overcome. for these pins, the desired function of the multi-functi on i/o pins is selected by a register via the application program control. pin-shared function selection registers the limited number of supplied pins in a package can i mpose restrictions on the amount of functions a certain device can contain. however by allowing the same pins to share several dif ferent functions and providing a means of function selection, a wide range of dif ferent functions can be incorporated into even relativel y small package sizes. this device includes pin-shared function selection register , labeled as psel, which can select the desired functions of the multi-function pin-shared pins. the m ost i mportant p oint t o n ote i s t o m ake sur e t hat t he d esired p in-shared f unction i s p roperly selected and also deselected. t o select the desired pin-shared function, the pin-shared function should frst be correctly selected using the corresponding pin-shared control register . after that the corresponding peripheral functional setting should be confgured and then the peripheral function can be enabled. t o correctly deselect the pin-shared function, the peripheral function should frst be disabled and then the corresponding pin-shared function control register can be modifed to select other pin-shared functions.
rev. 1.11 48 april 11, 2017 rev. 1.11 49 april 11, 2017 HT45F56 shock detector flash mcu HT45F56 shock detector flash mcu ? psel register bit 7 6 5 4 3 2 1 0 name psel5 psel4 psel3 psel2 psel1 psel0 r/w r/w r/w r/w r/w r/w r/w por 0 0 0 1 1 1 bit 7~6 unimplemented, read as 0 bit 5 psel5 : pa7 output type 0: cmos type 1: open drain type bit 4 psel4 : pa2 output type 0: cmos type 1: open drain type bit 3 psel3 : pa0 pin function selection 0: pa0 1: ctp bit 2 psel2 : pa6 pin function selection 0: pa6 1: ad2 bit 1 psel1 : pa5 pin function selection 0: pa5 1: sen bit 0 psel0 : pa1 pin function selection 0: pa1 1: ad1 i/o pin structures the accompanying diagrams illustrate the internal structures of some generic i/o pin types. as the exact logical construction of the i/o pin will dif fer from these drawings, they are supplied as a guide only to assist with the functional understanding of the i/o pins. the wide range of pin-shared structures does not permit all types to be shown.

??? ?? ? ? ? generic input/output structure
rev. 1.11 50 april 11, 2017 rev. 1.11 51 april 11, 2017 HT45F56 shock detector flash mcu HT45F56 shock detector flash mcu programming considerations within the user program, one of the things frs t to consider is port initialisation. after a res et, all of the i/o data and port control registers will be set to high. this means that all i/o pins will be defaulted to an input state, the level of which depends on the other connected circuitry and whether pull-high selections have been chosen. if the port control registers are then programmed to setup some pins as outputs, these output pins will have an initial high output value unless the associated port data registers are frst programmed. selecting which pins are inputs and which are outputs can be achieved byte-wide by loading the correct values into the appropriate port control register or by programming individual bits in the port control register using the set [m].i and clr [m].i instructions. note that when using these bit control instructions, a read-modify-write operation takes place. the microcontroller must frst read in the data on the entire port, modify it to the required new bit values and then rewrite this data back to the output ports. port a has the additional capability of providing wake-up functions. when the device is in the sleep or idle mode, various methods are available to wake the device up. one of these is a high to low transition of any of the port a pins. single or multiple pins on port a can be setup to have this function.
rev. 1.11 50 april 11, 2017 rev. 1.11 51 april 11, 2017 HT45F56 shock detector flash mcu HT45F56 shock detector flash mcu compact type timer module C ctm one of the most fundamental functions in any microcontroller devices is the ability to control and measure time. t o implement time related functions the device includes one t imer module, generally abbreviated to the name tm. this tm is the simplest type of the tms which contains a multi-purpose tim ing unit. although the simplest form of the tm types, the compact tm type still contains three operating modes, which are compare match output, t imer/event counter and pwm output modes. the compact tm can also be controlled with an external input pin and can drive one external output pin. the key to unders tanding how the tm operates is to s ee it in terms of a free running count-up counter whose value is then compared with the value of pre-programmed internal comparators. when the free running count-up counter has the same value as the pre-programmed comparator , known a s a c ompare m atch si tuation, a t m i nterrupt si gnal wi ll be ge nerated whi ch c an c lear t he counter and perhaps also change the condition of the tm output pin. the ctm has two interrupts, one for e ach of t he i nternal com parator a or com parator p , whi ch gene rate a tm inte rrupt whe n a compare match condition occurs. when a tm interrupt is generated, it can be used to clear the counter and also to change the state of the tm output pin. the i nternal t m c ounter i s dri ven by a use r se lectable c lock sourc e, wh ich c an be a n i nternal clock or a n e xternal pi n. t he se lection of t he re quired c lock sourc e i s i mplemented usi ng t he ctck2~ctck0 bits in the ctm control registers. the clock source can be a ratio of the system clock, f sys , or the internal high clock, f h , the f sub clock source or the external ctck pin. the ctck pin clock source is used to allow an external signal to drive the tm as an external clock source for event counting. the t m out put pi n c an be se lected usi ng t he c orresponding pi n-shared func tion se lection bi ts described in the pin-shared function section. when the tm is in the compare match output mode, these pins can be controlled by the tm to switch to a high or low level or to toggle when a compare match situation occurs. the external ctp output pin is also the pin where the tm generates the pwm output waveform. as the tm output pins are pin-shared with other functions, the tm output function must frst be setup using relevant pin-shared function selection register. ctm core ctm input pin ctm output pin 10-bit ctm ctck ctp f sys f sys /4 f h /64 f h /16 f sub ctck 000 001 010 011 100 101 110 111 ctck2~ctck0 10-bit count-up counter 3-bit comparator p ccrp b7~b9 b0~b9 10-bit comparator a cton ctpau comparator a match comparator p match counter clear 0 1 output control polarity control pin control ctp ctoc ctm1, ctm0 ctio1, ctio0 ctmaf interrupt ctmpf interrupt ctpol pin-shared control bit ccra ctcclr f sub compact type tm block diagram
rev. 1.11 52 april 11, 2017 rev. 1.11 53 april 11, 2017 HT45F56 shock detector flash mcu HT45F56 shock detector flash mcu compact tm operation the compact tm core is a 10-bit count-up counter which is driven by a user selectable internal or external clock source. there are also two internal comparators with the names, comparator a and comparator p . these comparators will compare the value in the counter with ccrp and ccra registers. the ccrp is three-bit w ide w hose value is compared w ith the highes t three bits in the counter while the ccra is ten-bit wide and therefore compares with all counter bits. the onl y way of changi ng the value of the 10-bit count er using the appl ication program , is to clear the counter by changing the ct on bit from low to high. the counter will also be cleared automatically by a counter overfow or a compare match with one of its associated comparators. when these conditions occur , a tm interrupt signal will also usually be generated. the compact type tm can operate in a number of dif ferent operational modes, can be driven by dif ferent clock sources including an input pin and can also control an output pin. all operating setup conditions are selected using relevant internal registers. compact type tm register description overall operation of the compact tm is controlled using a series of registers. a read only register pair e xists t o st ore t he i nternal c ounter 16 -bit va lue, whi le a re ad/write re gister pa ir e xists t o st ore the internal 10-bit ccra value. the remaining two registers are control registers which setup the different operating and control modes and as well as the three ccrp bits. register name bit 7 6 5 4 3 2 1 0 ctmc0 ctpau ctck2 ctck1 ctck0 cton ctrp2 ctrp1 ctrp0 ctmc1 ctm1 ctm0 ctio1 ctio0 ctoc ctpol ctdpx ctcclr ctmdl d7 d6 d5 d4 d3 d2 d1 d0 ctmdh d9 d8 ctmal d7 d6 d5 d4 d3 d2 d1 d0 ctmah d9 d8 10-bit compact tm registers list ctmdl register bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d3 d2 d1 d0 r/w r r r r r r r r por 0 0 0 0 0 0 0 0 bit 7~0 ctm counter low byte register bit 7 ~ bit 0 ctm 10-bit counter bit 7 ~ bit 0 ctmdh register bit 7 6 5 4 3 2 1 0 name d9 d8 r/w r r por 0 0 bit 7~2 unimplemented, read as 0 bit 1~0 ctm counter high byte register bit 1 ~ bit 0 ctm 10-bit counter bit 9 ~ bit 8
rev. 1.11 52 april 11, 2017 rev. 1.11 53 april 11, 2017 HT45F56 shock detector flash mcu HT45F56 shock detector flash mcu ctmal register bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 ctm ccra low byte register bit 7 ~ bit 0 ctm 10-bit ccra bit 7 ~ bit 0 ctmah register bit 7 6 5 4 3 2 1 0 name d9 d8 r/w r/w r/w por 0 0 bit 7~2 unimplemented, read as 0 bit 1~0 ctm ccra high byte register bit 1 ~ bit 0 ctm 10-bit ccra bit 9 ~ bit 8 ctmc0 register bit 7 6 5 4 3 2 1 0 name ctpau ctck2 ctck1 ctck0 cton ctrp2 ctrp1 ctrp0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 ctpau : ctm counter pause control 0: run 1: pause the c ounter c an be pa used by se tting t his bi t hi gh. cl earing t he bi t t o z ero re stores normal counter operation. when in a pause condition the ctm will remain powered up a nd c ontinue t o c onsume po wer. t he c ounter wi ll re tain i ts re sidual va lue whe n this bit changes from low to high and res ume counting from this value w hen the bit changes to a low value again. bit 6~4 ctck2~ctck0 : select ctm counter clock 000: f /4 001: f 010: f h /16 011: f h /64 100: f 101: f 110: ctck rising edge clock 111: ctck falling edge clock these three bits are used to select the clock source for the ctm. the external pin clock source can be chosen to be active on the rising or falling edge. the clock source is the system clock, while f h and f are other internal clocks, the details of which can be found in the oscillator section. bit 3 cton : ctm counter on/off control 0: off 1: on this bit controls the overall on/of f function of the ctm. setting the bit high enables the counter to run while clearing the bit disables the ctm. clearing this bit to zero will stop the counter from counting and turn of f the ctm which will reduce its power consumption. w hen t he b it c hanges st ate f rom l ow t o h igh t he i nternal c ounter v alue will be reset to zero, however when the bit changes from high to low , the internal counter will retain its residual value until the bit returns high again. if the ctm is in the compare match output mode then the ctm output pin will be reset to its initial condition, as specifed by the ctoc bit, when the cton bit changes from low to high.
rev. 1.11 54 april 11, 2017 rev. 1.11 55 april 11, 2017 HT45F56 shock detector flash mcu HT45F56 shock detector flash mcu bit 2~0 ctrp2~ctrp0 : ctm ccrp 3-bit register, compared with the ctm counter bit 9 ~ bit 7 000: 1024 ctm clocks 001: 128 ctm clocks 010: 256 ctm clocks 011: 384 ctm clocks 100: 512 ctm clocks 101: 640 ctm clocks 110: 768 ctm clocks 111: 896 ctm clocks these three bits are used to setup the value on the internal ccrp 3-bit register , which are then compared with the internal counter s highest three bits. the result of this comparison can be selected to clear the internal counter if the ctcclr bit is set to zero. setting the ctcclr bit to zero ensures that a compare match with the ccrp values will reset the internal counter . as the ccrp bits are only compared with the highest three counter bits, the compare values exist in 128 clock cycle multiples. clearing a ll t hree bi ts t o z ero i s i n e ffect a llowing t he c ounter t o ove rflow a t i ts maximum value. ctmc1 register bit 7 6 5 4 3 2 1 0 name ctm1 ctm0 ctio1 ctio0 ctoc ctpol ctdpx ctcclr r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~6 ctm1~ctm0 : select ctm operating mode 00: compare match output mode 01: undefned 10: pwm mode 11: t imer/counter mode these b its se tup t he r equired o perating m ode f or t he c tm. t o e nsure r eliable operation the ctm should be switched of f before any changes are made to the ctm1 and ctm0 bits. in the t imer/counter mode, the ctm output pin control will be disabled. bit 5~4 ctio1~ctio0 : select ctm external pin (ctp) function compare match output mode 00: no change 01: output low 10: output high 11: t oggle output pwm output mode 00: pwm output inactive state 01: pwm output active state 10: pwm output 11: undefned timer/counter mode unused these two bits are used to determin e how the ctm output pin changes state when a certain condition is reached. the function that these bits select depends upon in which mode the ctm is running.
rev. 1.11 54 april 11, 2017 rev. 1.11 55 april 11, 2017 HT45F56 shock detector flash mcu HT45F56 shock detector flash mcu in t he compa re ma tch out put mode, t he ctio1 a nd ctio0 bi ts det ermine how t he ctm output pin changes state when a compare match occurs from the comparator a. the ctm output pin can be setup to switch high, switch low or to toggle its present state when a compare match occurs from the comparator a. when the bits are both zero, then no change will take place on the output. the initial value of the ctm output pin should be setup using the ct oc bit in the ctmc1 register . note that the output level requested by the ctio1 and ctio0 bits must be dif ferent from the initial value setup using the ctoc bit otherwise no change will occur on the ctm output pin when a compare match occurs. after the ctm output pin changes state, it can be reset to its initial level by changing the level of the cton bit from low to high. in t he pw m mo de, t he c tio1 a nd c tio0 b its d etermine h ow t he c tm o utput p in changes state when a certain compare match condition occurs. the pwm output function i s m odified b y c hanging t hese t wo b its. i t i s n ecessary t o o nly c hange t he values of the ctio1 and ctio0 bits only after the ctm has been switched of f. unpredictable pwm output s wi ll oc cur i f t he ct io1 a nd ct io0 bi ts a re c hanged when the ctm is running. bit 3 ctoc : ctp output control compare match output mode 0: initial low 1: initial high pwm output mode 0: active low 1: active high this is the output control bit for the ctm output pin. its operation depends upon whether ctm is being used in the compare match output mode or in the pwm mode. it has no ef fect if the ctm is in the t imer/counter mode. in the compare match output mode it determines the logic level of the ctm output pin before a compare match occurs. in the pwm mode it determines if the pwm signal is active high or active low. bit 2 ctpol : ctp output polarity control 0: non-inverted 1: inverted this bit controls the polarity of the ctp output pin. when the bit is set high the ctm output pin will be inverted and not inverted when the bit is zero. it has no ef fect if the ctm is in the t imer/counter mode. bit 1 ctdpx : ctm pwm duty/period control 0: ccrp C period; ccra C duty 1: ccrp C duty; ccra C period this b it d etermines wh ich o f t he c cra a nd c crp r egisters a re u sed f or p eriod a nd duty control of the pwm waveform. bit 0 ctcclr : ctm counter clear condition selection 0: ctmn comparator p match 1: ctmn comparator a match this bi t i s use d t o se lect t he m ethod whi ch c lears t he c ounter. re member t hat t he compact tm contains two comparators, comparator a and comparator p , either of which can be selected to clear the internal counter . w ith the ctcclr bit set high, the counter will be cleared when a compare match occurs from the comparator a. when the bit is low , the counter will be cleared when a compare match occurs from the comparator p or with a counter overfow . a counter overfow clearing method can only be implemented if the ccrp bits are all cleared to zero. the ctcclr bit is not used in the pwm mode.
rev. 1.11 56 april 11, 2017 rev. 1.11 57 april 11, 2017 HT45F56 shock detector flash mcu HT45F56 shock detector flash mcu compact type tm operation modes the compact t ype tm can operate in one of three operating modes, compare match output mode, pwm mode or t imer/counter mode. the operating mode is selected using the ctm1 and ctm0 bits in the ctmc1 register. compare match output mode to select this mode, bits ctm1 and ctm0 in the ctmc1 register , should be set to 00 respectively. in this mode once the counter is enabled and running it can be cleared by three methods. these are a counter overfow , a compare match from comparator a and a compare match from comparator p . when the ctcclr bit is low , there are two ways in which the counter can be cleared. one is when a compare match occurs from comparator p , the other is when the ccrp bits are all zero which allows the counter to overfow . here both ctmaf and ctmpf interrupt request fags for the comparator a and comparator p respectively, will both be generated. if the ctcclr bit in the ctmc1 register is high then the counter will be cleared when a compare match occurs from comparator a. how ever, here only the ctma f interrupt request fag will be generated even if the value of the ccrp bits is less than that of the ccra registers. therefore when ctcclr is high no ctmpf interrupt request fag will be generated. if the ccra bits are all zero, the counter will overfow when its reaches its maximum 10-bit, 3ff hex, value, however here the ctmaf interrupt request fag will not be generated. as the name of the mode s uggests, after a comparis on is made, the ctm output pin w ill change state. the ctm output pin conditio n however only changes state when a ctmaf interrupt request fag is generated after a compare match occurs from comparator a. the ctmpf interrupt request fag, generated from a compare match occurs from comparator p , will have no ef fect on the ctm output pin. the way in which the ctm output pin changes state are determined by the condition of the ctio1 and ctio0 bits in the ctmc1 register . the ctm output pin can be selected using the ctio1 and ctio0 bits to go high, to go low or to toggle from its present condition when a compare match occurs from comparator a. the initial condition of the ctm output pin, which is setup after the ct on bit changes from low to high, is setup using the ct oc bit. note that if the ctio1 and ctio0 bits are zero then no pin change will take place.
rev. 1.11 56 april 11, 2017 rev. 1.11 57 april 11, 2017 HT45F56 shock detector flash mcu HT45F56 shock detector flash mcu counter value 0x3ff ccrp ccra cton ctpau ctpol ccrp int . flag ctmpf ccra int . flag ctmaf ctm o/p pin time ccrp=0 ccrp > 0 counter overflow ccrp > 0 counter cleared by ccrp value pause resume stop counter restart ctcclr = 0; ctm [1:0] = 00 output pin set to initial level low if ctoc=0 output toggle with ctmaf flag note ctio [1:0] = 10 active high output select here ctio [1:0] = 11 toggle output select output not affected by ctmaf flag. remains high until reset by cton bit output pin reset to initial value output controlled by other pin-shared function output inverts when ctpol is high compare match output mode C ctcclr = 0 note: 1. w ith ctcclr = 0, a comparator p match will clear the counter 2. the ctm output pin controlled only by ctmaf fag 3. the output pin is reset to its initial state by cton bit rising edge
rev. 1.11 58 april 11, 2017 rev. 1.11 59 april 11, 2017 HT45F56 shock detector flash mcu HT45F56 shock detector flash mcu counter value 0x3ff ccrp ccra cton ctpau ctpol ctm o / p pin time ccra=0 ccra = 0 counter overflow ccra > 0 counter cleared by ccra value pause resume stop counter restart ctcclr = 1; ctm [1:0] = 00 output pin set to initial level low if ctoc=0 output toggle with ctmaf flag note ctio [1:0] = 10 active high output select here ctio [1:0] = 11 toggle output select output not affected by ctmaf flag. remains high until reset by cton bit output pin reset to initial value output controlled by other pin-shared function output inverts when ctpol is high ctmpf not generated no ctmaf flag generated on ccra overflow output does not change ccra int . flag ctmaf ccrp int . flag ctmpf compare match output mode C ctcclr = 1 note: 1. w ith ctcclr = 1, a comparator a match will clear the counter 2. the ctm output pin is controlled only by ctmaf fag 3. the ctm output pin is reset to initial state by cton rising edge 4. the ctmpf fags is not generated when ctcclr = 1
rev. 1.11 58 april 11, 2017 rev. 1.11 59 april 11, 2017 HT45F56 shock detector flash mcu HT45F56 shock detector flash mcu timer/counter mode to select this mode, bits ctm1 and ctm0 in the ctmc1 register should be set to 1 1 respectively . the t imer/counter m ode operates in an identical w ay to the compare m atch o utput m ode generating the same interrupt flags. the exception is that in the t imer/counter mode the ctm output pin is not used. therefore the above description and t iming diagrams for the compare match output mode can be used to understand its function. as the ctm output pin is not used in this mode, the pin can be used as a normal i/o pin or other pin-shared function. pwm output mode to select this mode, bits ctm1 and ctm0 in the ctmc1 register should be set to 10 respectively . the pwm function within the ctm is useful for applications which require functions such as motor control, hea ting cont rol, i llumination cont rol et c. by provi ding a si gnal of fxe d frequenc y but of varying duty cycle on the ctm output pin, a square w ave a c w aveform can be generated w ith varying equivalent dc rms values. as both the period and duty cycle of the pwm waveform can be controlled, the choice of generated waveform is extremely fexible. in the pwm mode, the ctcclr bit has no ef fect on the pwm operation. bot h of t he ccra a nd ccrp re gisters a re use d t o ge nerate t he pw m wave form, one register is used to clear the internal counter and thus control the pwm waveform frequency , while the other one is used to control the duty cycle. which register is used to control either frequency or dut y cycle is determi ned using the ctdpx bit in the ctmc1 regi ster. the pwm waveform frequency and duty cycle can therefore be controlled by the values in the ccra and ccrp registers. an interrupt fag, one for each of the ccra and ccrp , will be generated when a compare match occurs from either comparator a or comparator p . the ct oc bit in the ctmc1 register is used to select the required polarity of the pwm waveform while the two ctio1 and ctio0 bits are used to enable the pwm output or to force the tm output pin to a fxed high or low level. the ctpol bit is used to reverse the polarity of the pwm output waveform. ? 10-bit ctm, pwm mode, edge-aligned mode, ctdpx=0 ccrp 001b 011b 011b 100b 101b 110b 111b 000b period 128 256 384 512 640 768 896 1024 duty ccra if f sys = 8mhz, ctm clock source is f sys /4, ccrp = 2 and ccra = 128, the ctm pwm output frequency = (f sys /4) / (2x256) = f sys /2048 = 4 khz, duty = 128/(2x256)= 25%. if the duty value defned by the ccra register is equal to or greater than the period value, then the pwm output duty is 100%. ? 10-bit ctm, pwm mode, edge-aligned mode, ctdpx=1 ccrp 001b 011b 011b 100b 101b 110b 111b 000b period ccra duty 128 256 384 512 640 768 896 1024 the pw m out put pe riod i s de termined by t he ccra re gister va lue t ogether wi th t he ct m c lock while the pwm duty cycle is defned by the ccrp register value.
rev. 1.11 60 april 11, 2017 rev. 1.11 61 april 11, 2017 HT45F56 shock detector flash mcu HT45F56 shock detector flash mcu counter value ccrp ccra cton ctpau ctpol ctm o / p pin ( ctoc =1) time counter cleared by ccrp pause resume counter stop if cton bit low counter reset when cton returns high ctdpx = 0; ctm [1:0] = 10 pwm duty cycle set by ccra pwm resumes operation output controlled by other pin-shared function output inverts when ctpol = 1 pwm period set by ccrp ctm o / p pin ( ctoc =0) ccra int . flag ctmaf ccrp int . flag ctmpf pwm output mode C ctdxp = 0 note: 1. here ctdpx = 0 C counter cleared by ccrp 2. a counter clear sets pwm period 3. the internal pwm function continues even when ctio1, ctio0 = 00 or 01 4. the ctcclr bit has no infuence on pwm operation
rev. 1.11 60 april 11, 2017 rev. 1.11 61 april 11, 2017 HT45F56 shock detector flash mcu HT45F56 shock detector flash mcu counter value ccrp ccra cton ctpau ctpol ccrp int . flag ctmpf ccra int . flag ctmaf ctm o / p pin ( ctoc =1) time counter cleared by ccra pause resume counter stop if cton bit low counter reset when cton returns high ctdpx = 1; ctm [1:0] = 10 pwm duty cycle set by ccrp pwm resumes operation output controlled by other pin-shared function output inverts when ctpol = 1 pwm period set by ccra ctm o / p pin ( ctoc =0) pwm output mode C ctdxp = 1 note: 1. here ctdpx = 1 C counter cleared by ccra 2. a counter clear sets pwm period 3. the internal pwm function continues even when ctio [1:0] = 00 or 01 4. the ctcclr bit has no infuence on pwm operation
rev. 1.11 62 april 11, 2017 rev. 1.11 63 april 11, 2017 HT45F56 shock detector flash mcu HT45F56 shock detector flash mcu programming considerations the tm counter registers and the capture/compare ccra registers, all have a low and high byte structure. the high bytes can be directly accessed, but as the low bytes can only be accessed via an internal 8-bit buf fer, reading or writing to these register pairs must be carried out in a specifc way . the important point to note is that data transfer to and from the 8-bit buf fer and its related low byte only takes place when a write or read operation to its corresponding high byte is executed. as the ccra registers is implemented in the way shown in the following diagram and accessing these register pairs is carried out in a specifc way as described above, it is recommended to use the mov instruction to access the ccra low byte registers, named ctmal, using the following access procedure s. ac cessing t he ccra l ow byte regi sters wi thout foll owing t hese ac cess procedures will result in unpredictable values. data bus 8-bit buffer ctmdh ctmdl ctmah ctmal ctm counter register (read only) ctm ccra register (read/write) the following steps show the read and write procedures: ? writing data to ccra ? step 1. w rite data to low byte ctmal C note that here data is only written to the 8-bit buffer. ? step 2. w rite data to high byte ctmah C here data is written directly to the high byte regis ters and simultaneously data is latched from the 8-bit buffer to the low byte registers. ? reading data from the counter registers and ccra ? step 1. read data from the high byte ctmdh or ctmah C here d ata i s r ead d irectly f rom t he hi gh b yte r egisters a nd si multaneously d ata i s l atched from the low byte register into the 8-bit buffer. ? step 2. read data from the low byte ctmdl or ctmal C this step reads data from the 8-bit buffer.
rev. 1.11 62 april 11, 2017 rev. 1.11 63 april 11, 2017 HT45F56 shock detector flash mcu HT45F56 shock detector flash mcu digital to analog converter there i s a 6-bi t r-2r di gital t o ana log c onverter i ntegrated i n t his de vice. t he di gital da ta t o be converted is stored in the dacr register . the d/a converter output can be used as the reference voltage applied on the negative input of the comparator . the dacen bit is used to control the d/a converter function. register name bit 7 6 5 4 3 2 1 0 dacr dacen da5 da4 da3 da2 da1 da0 opac opaen cks1 cks0 digital to analog converter registers list dacr register bit 7 6 5 4 3 2 1 0 name dacen da5 da4 da3 da2 da1 da0 r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 bit 7 dacen : d/a converter enable control 0: disable 1: enable bit 6 unimplemented, read as 0 bit 5~0 da5~da0 : d/a converter digital data bit 5 ~ bit 0 [ ] 64 vda0~da5 voltage output d/a dd = opac register bit 7 6 5 4 3 2 1 0 name opaen cks1 cks0 r/w r/w r/w r/w por 1 0 0 bit 7 unimplemented, read as 0 bit 6 opaen : operational amplifer enable control described elsewhere. bit 5~2 unimplemented, read as 0 bit 1~0 cks1~cks0 : d/a converter clock source selection 00: f lirc /4 01~11: reserved, can not be used.
rev. 1.11 64 april 11, 2017 rev. 1.11 65 april 11, 2017 HT45F56 shock detector flash mcu HT45F56 shock detector flash mcu operational amplifer this de vice cont ains an operational ampli fier with programma ble gain selec tions, which is use d to a mplify t he sm all a nalog i nput si gnal. af ter a mplification t he out put si gnal c an be se nt t o t he comparator positive input to compare with the negative input signal. the overall function is controlled by the opac and opga registers. register name bit 7 6 5 4 3 2 1 0 opac opaen cks1 cks0 opga gas3 gas2 gas1 gas0 operational amplifer registers list opac register bit 7 6 5 4 3 2 1 0 name opaen cks1 cks0 r/w r/w r/w r/w por 1 0 0 bit 7 unimplemented, read as 0 bit 6 opaen : operational amplifer enable control 0: disable 1: enable bit 5~2 unimplemented, read as 0 bit 1~0 cks1~cks0 : d/a converter clock source selection described elsewhere. opga register bit 7 6 5 4 3 2 1 0 name gas3 gas2 gas1 gas0 r/w r/w r/w r/w r/w por 1 1 1 1 bit 7~4 unimplemented, read as 0 bit 3~0 gas3~gas0 : operational amplifer gain selection 0000: gain = 1 0100: gain = 10 1000: gain = 15 1100: gain = 25 0001: gain = 10 0101: gain = 100 1001: gain = 150 1101: gain = 250 0010: gain = 30 0110: gain = 300 1010: gain = 450 1110: gain = 750 0011: gain = 40 0111: gain = 400 1011: gain = 600 1111: gain = 1000
rev. 1.11 64 april 11, 2017 rev. 1.11 65 april 11, 2017 HT45F56 shock detector flash mcu HT45F56 shock detector flash mcu comparators the devi ce cont ains an analog comparat or which operates wit h the 6-bit r-2r d/a converter and operational amplif er in applications . these functions of fer fexibility via the corresponding registers controlled features such as power -down, hysteresis, etc. in sharing their pins with normal i/o pins the comparator does not waste precious i/o pins if their functions are otherwise unused. ad1 ad2 + ? cmpen cmpop debounce circuit debounce interrupt cmphy[1:0] pin-shared select m u x 6-bit d/a da[5:0] cnsel[1:0] m u x cpsel[1:0] sen opa gas[3:0] opaen dstag[2:0] comparator interrupt comparator block diagram comparator operation the comparator functions are used to compare two analog voltages and provide an output based on their input dif ference. any pull-high resistors connected to the shared comparator input pins will be automatically disconnected when the corresponding comparator functional pins are selected. as the comparator i nputs a pproach t heir swi tching l evel, so me sp urious o utput si gnals m ay b e g enerated on the comparator output due to the slow rising or falling nature of the input signals. this can be minimised by the hysteresi s func tion. ide ally t he com parator shoul d swi tch at t he point where t he positive and negative inputs signals are at the same voltage level. however , unavoidable input offsets introduce some uncertainties here. the hysteresis function, if enabled, will also increase the switching offset value. the hysteresis window will be changed for different selections. an interrupt will be generated when the comparator output changes state from low to high. another interrupt will be generated when the comparator output rising edge transition occurs and keeps more than a certain debounce time determined by the dst ag2~dstag0 bits. if the comparator output rising edge transit ion occurs but does not keep more than the specifc debounce time, the debounce circuit interrupt will not be generated. comparator registers full control over the internal comparator is provided via the control registers, cmpc, muxc and debc. the comparator output is recorded via a bit in the respective control register. the comparator power down control bit, cmpen, is used to control the overall comparator function. register name bit 7 6 5 4 3 2 1 0 cmpc cmpop cmphy1 cmphy0 cmpen muxc cnsel1 cnsel0 cpsel1 cpsel0 debc dstag2 dstag1 dstag0 comparator registers list
rev. 1.11 66 april 11, 2017 rev. 1.11 67 april 11, 2017 HT45F56 shock detector flash mcu HT45F56 shock detector flash mcu cmpc register bit 7 6 5 4 3 2 1 0 name cmpop cmphy1 cmphy0 cmpen r/w r r/w r/w r/w por x 0 0 1 x: unknown bit 7 cmpop : comparator output status 0: positive input voltage < negative input voltage 1: positive input voltage > negative input voltage this bit is read-only and used to store compatarot output status. bit 6 unimplemented, read as 0. bit 5~4 cmphy1~cmphy0 : comparator hysteresis selection 00: 0mv 01: 25mv 10: 50mv 11: 75mv bit 3~1 unimplemented, read as 0 bit 0 cmpen : comparator enable control 0: disable 1: enable muxc register bit 7 6 5 4 3 2 1 0 name cnsel1 cnsel0 cpsel1 cpsel0 r/w r/w r/w r/w r/w por 0 0 0 0 x: unknown bit 7~6 unimplemented, read as 0 bit 5~4 cnsel1~cnsel0 : comparator negative input selection 00: ad2 01: ad1 1x: dac output bit 3~2 unimplemented, read as 0 bit 1~0 cpsel1~cpsel0 : comparator positive input selection 00: opa output 01: ad1 1x: ad2 debc register bit 7 6 5 4 3 2 1 0 name dstag2 dstag1 dstag0 r/w r/w r/w r/w por 0 0 0 bit 7~3 unimplemented, read as 0 bit 2~0 dstag2~dstag0 : debounce time selection 000: no debounce 001: 4 f lirc clock cycles 010: 8 f lirc clock cycles 011: 16 f lirc clock cycles 100: 32 f lirc clock cycles 101: 64 f lirc clock cycles 110: 128 f lirc clock cycles 111: 128 f lirc clock cycles
rev. 1.11 66 april 11, 2017 rev. 1.11 67 april 11, 2017 HT45F56 shock detector flash mcu HT45F56 shock detector flash mcu interrupts interrupts are an important part of any microcontroller s ystem. when an external event or an internal function such as a t imer module or an a/d converter requires microcontroller attention, their corresponding interrupt will enforce a temporary suspension of the main program allowing the microcontroller to direct attention to their respective needs. these devices contain several external interrupt and internal interrupts functions . the external interrupts are generated by the action of the external int0 and int1 pins, while the internal interrupts are generated by various internal functions such as the tms, t ime base, eeprom, comparator and debounce circuit. interrupt registers overall interrupt control, w hich bas ically means the s etting of reques t flags w hen certain microcontroller conditions occur and the setting of interrupt enable bits by the application program, is controlled by a s eries of regis ters, located in the s pecial p urpose d ata m emory, as s hown in the accompanying table. thes e registers are the intc0~intc2 registers which setup the primary interrupts. each register contains a number of enable bits to enable or disable individual interrupts as well as i nterrupt fa gs t o i ndicate t he p resence o f a n i nterrupt r equest. t he n aming c onvention o f t hese follows a specifc pattern. first is listed an abbreviated interrupt type, then the (optional) number of that interrupt followed by either an e for enable/disable bit or f for request fag. function enable bit request flag notes global emi comparator cpe cpf debounce debe debf time base tbne tbnf n = 0 ~ 1 eeprom write operation dee def ctm ctmpe ctmpf ctmae ctmaf interrupt register bit naming conventions register name bit 7 6 5 4 3 2 1 0 intc0 tb0f debf cpf tb0e debe cpe emi intc1 tb1f def ctmaf ctmpf tb1e dee ctmae ctmpe interrupt registers list
rev. 1.11 68 april 11, 2017 rev. 1.11 69 april 11, 2017 HT45F56 shock detector flash mcu HT45F56 shock detector flash mcu intc0 register bit 7 6 5 4 3 2 1 0 name tb0f debf cpf tb0e debe cpe emi r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 bit 7 unimplemented, read as 0 bit 6 tb0f : t ime base 0 interrupt request fag 0: no request 1: interrupt request bit 5 debf : debounce circuit interrupt request fag 0: no request 1: interrupt request bit 4 cpf : comparator interrupt request fag 0: no request 1: interrupt request bit 3 tb0e : t ime base 0 interrupt control 0: disable 1: enable bit 2 debe : debounce circuit interrupt control 0: disable 1: enable bit 1 cpe : comparator interrupt control 0: disable 1: enable bit 0 emi : global interrupt control 0: disable 1: enable
rev. 1.11 68 april 11, 2017 rev. 1.11 69 april 11, 2017 HT45F56 shock detector flash mcu HT45F56 shock detector flash mcu intc1 register bit 7 6 5 4 3 2 1 0 name tb1f def ctmaf ctmpf tb1e dee ctmae ctmpe r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 tb1f : t ime base 1 interrupt request fag 0: no request 1: interrupt request bit 6 def : data eeprom interrupt request fag 0: no request 1: interrupt request bit 5 ctmaf : ctm comparator a match interrupt request fag 0: no request 1: interrupt request bit 4 ctmpf : ctm comparator p match interrupt request fag 0: no request 1: interrupt request bit 3 tb1e : t ime base 1 interrupt control 0: disable 1: enable bit 2 dee : data eeprom interrupt control 0: disable 1: enable bit 1 ctmae : ctm comparator a match interrupt control 0: disable 1: enable bit 0 ctmpe : ctm comparator p match interrupt control 0: disable 1: enable interrupt operation when the conditions for an interrup t event occur , such as a tm comparator p or comparator a or comparator output transition, etc, the relevant interrupt request fag will be set. whether the request fag actually generates a program jump to the relevant interrupt vector is determined by the condition of t he i nterrupt e nable bi t. if t he e nable bi t i s se t hi gh t hen t he progra m wi ll j ump t o i ts re levant vector; if the enable bit is zero then although the interrupt request fag is set an actual interrupt will not be generated and the program will not jump to the relevant interrupt vector . the global interrupt enable bit, if cleared to zero, will disable all interrupts. when an interrupt is generated, the program counter, which stores the address of the next instruction to be executed, will be transferred onto the stack. the program counter will then be loaded with a new address which will be the value of the corresponding interrupt vector . the microcontroller will then fetch its next instruction from this interrupt vector . the instruction at this vector will usually be a jmp which will jump to another section of program which is known as the interrupt service routine. here is located the code to control the appropriate interrupt. the interrupt service routine must be terminated with a reti, which retrieves the original program counter address from the stack and allow s the microcontroller to continue w ith normal execution at the point w here the interrupt occurred.
rev. 1.11 70 april 11, 2017 rev. 1.11 71 april 11, 2017 HT45F56 shock detector flash mcu HT45F56 shock detector flash mcu the various interrupt enable bits, together with their associated request flags, are shown in the accompanying diagrams with their order of priority . some interrupt sources have their own individual vector w hile others s hare the s ame multi-function interrupt vector . o nce an interrupt subroutine is serviced, all other interrupts will be blocked, as the global interrupt enable bit, emi bit will be cleared automatically . this will prevent any further interrupt nesting from occurring. however, i f ot her i nterrupt re quests oc cur duri ng t his i nterval, a lthough t he i nterrupt wi ll not be immediately serviced, the request fag will still be recorded. if an interrupt requires immediate servicing while the program is alread y in another interrupt service routine, the emi bit should be set after entering the routine to allow interrupt nesting. if the stack is full, the interrupt request will not be acknowledged, even if the related interrupt is enabled, until the stack pointer is decremented. if immediate service is desired, the stack must be prevented from becoming full. in case of simultaneous requests, the accompanying diagram shows the priority that is a pplied. al l o f t he i nterrupt r equest fa gs wh en se t wi ll wa ke u p t he d evice i f i t i s i n sl eep o r idle mode, however to prevent a wake-up from occurring the corresponding fag should be set before the device is in sleep or idle mode. comparator cpf cpe emi 04h emi 08h debounce debf debe emi 0ch emi 10h time base 0 tb0f tb0e emi 14h emi 18h interrupt name request flags enable bits master enable vector emi auto disabled in isr priority high low emi 1ch time base 1 tb1f tb1e ctm p ctmpf ctmpe ctm a ctmaf ctmae eeprom def dee xxe enable bits xxf request flag, auto reset in isr legend interrupt structure comparator interrupt the comparator interrupt is control led by the comparator output transition. a comparator interrupt request will take place when the comparator interrupt request fag, cpf , is set, which occurs when the comparator output changes state. t o allow the program to branch to its respective int errupt vector address, the global interrupt enable bit, emi, and comparator interrupt enable bit, cpe, must frst be set. when the interrupt is enabled, the stack is not full and the comparator output transition occurs, a subroutine call to the comparator int errupt vector will take place. when the interrupt is serviced, the comparator interrupt fag, cpf , will be automatically clea red. the emi bit will also be automatically cleared to disable other interrupts.
rev. 1.11 70 april 11, 2017 rev. 1.11 71 april 11, 2017 HT45F56 shock detector flash mcu HT45F56 shock detector flash mcu debounce interrupt the debounce interrupt is controlled by the debounce circuit output transition. a debounce interrupt r equest wi ll t ake p lace wh en t he de bounce i nterrupt r equest f lag, de bf, i s se t, wh ich occurs when the debounce circuit output changes state. t o allow the program to branch to its respective i nterrupt vec tor address, t he globa l i nterrupt ena ble bit , emi, and compara tor inte rrupt enable bit, debe, must first be set. when the interrupt is enabled, the stack is not full and the debounce c ircuit out put t ransition oc curs, a subrout ine c all t o t he de bounce int errupt ve ctor wi ll take place. when the interrupt is serviced, the debounce interrupt fag, debf , will be automatically cleared. the emi bit will also be automatically cleared to disable other interrupts. time base interrupt the function of the t ime base interrupt is to provide regular time signal in the form of an internal interrupt. it i s c ontrolled by t he ove rflow si gnal from i ts i nternal t imer. w hen t his ha ppens i ts interrupt re quest fag, tbnf , will be set. t o allow the program to branch to its respective interrupt vector addresses, the global interrupt enable bit, emi and t ime base enable bit, tbne, must frst be set. when the interrupt is enabled, the stack is not full and the t ime base overfows, a subroutine call to its respective vector location will take place. when the interrupt is serviced, the interrupt request fag, tbnf , will be automatically reset and the emi bit will be cleared to disable other interrupts. the purpose of the t ime base interrupt is to provide an interrupt signal at fxed time periods. its clock s ource, f tb , originates from the internal clock s ource f sys /4 or f tbc and then pass es through a di vider, t he di vision ra tio of whi ch i s se lected by progra mming t he a ppropriate bi ts i n t he t bc register to obtain longer interrupt periods whose value ranges. the clock source which in turn controls the t ime base interrupt period is selected using the tbck bit in the tbc register. m u x f sys /4 f tbc 1/2 8 ~1/2 15 tbck f tb tb 0[2:0] tb 1[1:0] time base 0 interrupt time base 1 interrupt 1/2 12 ~1/2 15 time base interrupts
rev. 1.11 72 april 11, 2017 rev. 1.11 73 april 11, 2017 HT45F56 shock detector flash mcu HT45F56 shock detector flash mcu tbc register bit 7 6 5 4 3 2 1 0 name tbon tbck tb11 tb10 tb02 tb01 tb00 r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 1 1 1 1 1 bit 7 tbon : t ime base function enable control 0: disable 1: enable bit 6 tbck : t ime base clock source f tb selection 0: f tbc 1: f sys /4 bit 5~4 tb11~tb10 : t ime base 1 time-out period selection 00: 2 12 /f tb 01: 2 13 /f tb 10: 2 14 /f tb 11: 2 15 /f tb bit 3 uimplemented, read as 0 bit 2~0 tb02~tb00 : t ime base 0 time-out period selection 000: 2 8 /f tb 001: 2 9 /f tb 010: 2 10 /f tb 011: 2 11 /f tb 100: 2 12 /f tb 101: 2 13 /f tb 110: 2 14 /f tb 111: 2 15 /f tb eeprom interrupt the e eprom w rite i nterrupt i s c ontrolled b y t he e eprom w rite o peration c ompletion. an eeprom w rite interrupt request will take place when the eeprom w rite interrupt request fag, def, is set, which occurs when an eeprom w rite cycle ends. t o all ow the program to branch to its r espective i nterrupt v ector a ddress, t he g lobal i nterrupt e nable b it, e mi, a nd e eprom w rite interrupt enable bit, dee, must frst be set. when the interrupt is enabled, the stack is not full and an eeprom w rite cycle ends, a subroutine call to the respective eeprom w rite interrupt vector will take plac e. when the eeprom w rite interrupt is serviced, the comparator interrupt fag, def , will be automatically cleared. the emi bit will also be automatically cleared to disable other interrupts. tm interrupts the compact tms have two interru pts, one comes from the comparat or a match situation and the other comes from the comparator p match situation. a tm interrupt request will take place when any of the tm request fags are set, a situation which occurs when a tm comparator p or a match situation happens. to allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, and respective tm interrupt enable bit, must frst be set. when the interrupt is enabled, the stack is not full and a tm comparat or match situation occurs, a subroutine call to the relevant ctm interrupt v ector l ocations, wi ll t ake p lace. w hen t he t m i nterrupt i s se rviced, t he c orresponding ctm interrupt request fag will be automatically cleared. the emi bit will also be automatically cleared to disable other interrupts.
rev. 1.11 72 april 11, 2017 rev. 1.11 73 april 11, 2017 HT45F56 shock detector flash mcu HT45F56 shock detector flash mcu interrupt wake-up function each of the int errupt funct ions has the capa bility of waki ng up the mi crocontroller when in the sleep o r i dle mo de. a wa ke-up i s g enerated wh en a n i nterrupt r equest fa g c hanges f rom l ow to high and is independent of whether the interrupt is enabled or not. therefore, even though these devices are in the sleep or idle mode and its system oscillator stopped, situations such as external edge transitions on the external interrupt pins, a low power supply voltage or comparator input change may cause their respective interrupt fl ag to be set hi gh and consequently generate an i nterrupt. c are m ust t herefore b e t aken i f sp urious wa ke-up si tuations a re t o b e a voided. i f a n interrupt wake-up function is to be disabled then the corresponding interrupt request fag should be set high before the device enters the sleep or idle mode. the interr upt enable bits have no ef fect on the interrupt wake-up function. programming considerations by di sabling t he re levant i nterrupt e nable bi ts, a re quested i nterrupt c an be pre vented from be ing serviced, however , once an interrupt request flag is set, it will remain in this condition in the interrupt register until the corresponding interrupt is serviced or until the request fag is cleared by the application program. it is recommended that programs do not use the call instruction within the interrupt service subroutine. interrupts often occur in an unpredictable manner or need to be serviced immediately . if only one stack is left and the inte rrupt is not well controlled, the original control sequence will be damaged once a call subroutine is executed in the interrupt subroutine. every interrupt has the capability of waking up the microcontroller when it is in the sleep or idle mode, the wake up being generated when the interrupt request fag changes from low to high. if it is required to prevent a certain interru pt from waking up the microcontrol ler then its respective request fag should be frst set high before enter sleep or idle mode. as only the program counter is pushed onto the stack, then when the interrupt is serviced, if the contents of the accumulator , status register or other registers are altered by the interrupt service program, t heir c ontents shoul d be sa ved t o t he m emory a t t he be ginning of t he i nterrupt se rvice routine. to return from an interrupt subroutine, either a ret or reti instruction may be executed. the reti instruction in addition to executing a return to the main program also automatically sets the emi bit high to allow further interrupts. the ret instruction however only executes a return to the main program leaving the emi bit in its present zero state and therefore disabling the execution of further interrupts.
rev. 1.11 74 april 11, 2017 rev. 1.11 75 april 11, 2017 HT45F56 shock detector flash mcu HT45F56 shock detector flash mcu application circuits sense magnetic sensor module signal by sen pin ht 45 f 56 vdd v dd vss pa 0 pa 7/ res pa 2 pa 1/ ad 1 pa 6/ ad 2 pa 5/ sen 0.1f s n magnet sensor 0.1f
rev. 1.11 74 april 11, 2017 rev. 1.11 75 april 11, 2017 HT45F56 shock detector flash mcu HT45F56 shock detector flash mcu instruction set introduction central to the successful operation of any microcontroller is its instruction set, which is a set of program instruction codes that direc ts the microcontroller to perform certain operations. in the case of holtek microcontroller , a comprehensive and fexible set of over 60 instructions is provided to enable programmers to implement their application with the minimum of programming overheads. for easier understanding of the various instruction codes, they have been subdivided into several functional groupings. instruction timing most instructions are implemented within one instruction cycle. the exceptions to this are branch, call, or table read instructions where two ins truction cycles are required. one instruction cycle is equal to 4 system clock cycles, therefore in the case of an 8mhz system oscillator , most instructions would be i mplemented wi thin 0.5 s a nd bra nch or c all i nstructions woul d be i mplemented wi thin 1s. although instructions which require one more cycle to implement are generally limited to the jmp , call, ret , reti and table read instructions, it is important to realize that any other instructions which involve manipulation of the program counter low register or pcl will also take one more cycle to implement. as instructions which change the contents of the pcl will imply a direct j ump t o t hat ne w a ddress, one m ore c ycle wi ll be re quired. e xamples of suc h i nstructions would be "clr pcl" or "mov pcl, a". for the case of skip instructions, it must be noted that if the result of the comparison involves a skip operation then this will also take one more cycle, if no skip is involved then only one cycle is required. moving and transferring data the t ransfer of da ta wi thin t he m icrocontroller progra m i s one of t he m ost fre quently use d operations. making use of three kinds of mov instructions, data can be transferred from registers to the accumulator and vice-versa as well as being able to move specifc immediate data directly into the ac cumulator. one of t he m ost i mportant da ta t ransfer a pplications i s t o re ceive da ta from t he input ports and transfer data to the output ports. arithmetic operations the ability to perform certain arithm etic operations and data manipula tion is a necessary feature of most m icrocontroller a pplications. w ithin t he hol tek m icrocontroller i nstruction se t a re a ra nge of add and subtract instruction mnemonics to enable the necessary arithmetic to be carried out. care must be taken to ens ure correct handling of carry and borrow data w hen res ults exceed 255 for addition and less than 0 for subtraction. the increment and decrement instructions inc, inca, dec and deca provide a simple means of increasing or decreasing by a value of one of the values in the destination specifed.
rev. 1.11 76 april 11, 2017 rev. 1.11 77 april 11, 2017 HT45F56 shock detector flash mcu HT45F56 shock detector flash mcu logical and rotate operation the standard logical operations such as and, or, xor and cpl all have their own instruction within t he hol tek m icrocontroller i nstruction se t. as wi th t he c ase of m ost i nstructions i nvolving data m anipulation, d ata m ust p ass t hrough t he ac cumulator wh ich m ay i nvolve a dditional programming steps. in all logical data operations, the zero flag may be set if the result of the operation is zero. another form of logical data manipulation comes from the rotate instructions such as rr, rl, rrc and rlc which provide a simple means of rotating one bit right or left. dif ferent rotate instructions exist depending on program requirements. rotate instructions are useful for serial port progra mming a pplications whe re da ta c an be rot ated from a n i nternal re gister i nto t he ca rry bit from where it can be examined and the necessary serial bit set high or low . another application which rotate data operations are used is to implement multiplication and division calculations. branches and control transfer program branching takes the form of either jumps to specifed locations using the jmp instruction or t o a su broutine usi ng t he cal l i nstruction. t hey di ffer i n t he se nse t hat i n t he c ase of a subroutine call, the program mus t return to the ins truction immediately w hen the s ubroutine has been carried out. this is done by placing a return ins truction " ret" in the s ubroutine w hich w ill cause the program to jump back to the address right after the call instruction. in the case of a jmp instruction, the program simply jumps to the desired location. there is no requirement to jump back to the original jumping of f point as in the case of the call instruction. one special and extremely useful set of branch instructions are the conditional branches. here a decision is frst made regarding the c ondition of a c ertain da ta m emory or i ndividual bi ts. de pending upon t he c onditions, t he program will continue with the next instruction or skip over it and jump to the following instruction. these i nstructions a re t he ke y t o de cision m aking a nd bra nching wi thin t he progra m pe rhaps determined by the condition of certain input switches or by the condition of internal data bits. bit operations the abili ty to provide single bit operations on data memory is an extremely fexible feature of all holtek microcontrollers . this feature is especially useful for output port bit programming where individual bits or port pins can be directly set high or low using either the "set [m].i" or "clr [m]. i" instructions respectively . the feature removes the need for programmers to frst read the 8-bit output port, manipulate the input data to ensure that other bits are not changed and then output the port with the correct new data. this read-modify-write process is take n care of automatically when these bit operation instructions are used. table read operations data st orage i s norm ally i mplemented by usi ng re gisters. however , whe n worki ng wi th l arge amounts of fxed data, the volume involved often makes it inconvenient to store the fxed data in the data memory . t o overcome this problem, holtek microcontrollers allow an area of program memory to be set as a table where data can be directly stored. a set of easy to use instructions provides the means by w hich this fixed data can be referenced and retrieved from the program memory. other operations in addition to the above functional instructions, a range of other instructions also exist such as the "hal t" i nstruction f or po wer-down o perations a nd i nstructions t o c ontrol t he o peration o f the w atchdog t imer for reliable program operations under extreme electric or electromagnetic environments. for their relevant operations, refer to the functional related sections.
rev. 1.11 76 april 11, 2017 rev. 1.11 77 april 11, 2017 HT45F56 shock detector flash mcu HT45F56 shock detector flash mcu instruction set summary the following table depicts a summary of the instruction set categorised according to function and can be consulted as a basic instruction reference using the following listed conventions. table conventions x: bits immediate data m: data memory address a: accumulator i: 0~7 number of bits addr: program memory address mnemonic description cycles flag affected arithmetic add a,[m] add data memory to acc 1 z, c, ac, ov addm a,[m] add acc to data memory 1 note z, c, ac, ov add a,x add immediate data to acc 1 z, c, ac, ov adc a,[m] add data memory to acc with carry 1 z, c, ac, ov adcm a,[m] add acc to data memory with carry 1 note z, c, ac, ov sub a,x subtract immediate data from the acc 1 z, c, ac, ov sub a,[m] subtract data memory from acc 1 z, c, ac, ov subm a,[m] subtract data memory from acc with result in data memory 1 note z, c, ac, ov sbc a,[m] subtract data memory from acc with carry 1 z, c, ac, ov sbcm a,[m] subtract data memory from acc with carry, result in data memory 1 note z, c, ac, ov daa [m] decimal adjust acc for addition with result in data memory 1 note c logic operation and a,[m] logical and data memory to acc 1 z or a,[m] logical or data memory to acc 1 z xor a,[m] logical xor data memory to acc 1 z andm a,[m] logical and acc to data memory 1 note z orm a,[m] logical or acc to data memory 1 note z xorm a,[m] logical xor acc to data memory 1 note z and a,x logical and immediate data to acc 1 z or a,x logical or immediate data to acc 1 z xor a,x logical xor immediate data to acc 1 z cpl [m] complement data memory 1 note z cpla [m] complement data memory with result in acc 1 z increment & decrement inca [m] increment data memory with result in acc 1 z inc [m] increment data memory 1 note z deca [m] decrement data memory with result in acc 1 z dec [m] decrement data memory 1 note z rotate rra [m] rotate data memory right with result in acc 1 none rr [m] rotate data memory right 1 note none rrca [m] rotate data memory right through carry with result in acc 1 c rrc [m] rotate data memory right through carry 1 note c rla [m] rotate data memory left with result in acc 1 none rl [m] rotate data memory left 1 note none rlca [m] rotate data memory left through carry with result in acc 1 c rlc [m] rotate data memory left through carry 1 note c
rev. 1.11 78 april 11, 2017 rev. 1.11 79 april 11, 2017 HT45F56 shock detector flash mcu HT45F56 shock detector flash mcu mnemonic description cycles flag affected data move mov a,[m] move data memory to acc 1 none mov [m],a move acc to data memory 1 note none mov a,x move immediate data to acc 1 none bit operation clr [m].i clear bit of data memory 1 note none set [m].i set bit of data memory 1 note none branch operation jmp addr jump unconditionally 2 none sz [m] skip if data memory is zero 1 note none sza [m] skip if data memory is zero with data movement to acc 1 note none sz [m].i skip if bit i of data memory is zero 1 note none snz [m].i skip if bit i of data memory is not zero 1 note none siz [m] skip if increment data memory is zero 1 note none sdz [m] skip if decrement data memory is zero 1 note none siza [m] skip if increment data memory is zero with result in acc 1 note none sdza [m] skip if decrement data memory is zero with result in acc 1 note none call addr subroutine call 2 none ret return from subroutine 2 none ret a,x return from subroutine and load immediate data to acc 2 none reti return from interrupt 2 none table read operation tabrd [m] read table (specifc page) to tblh and data memory 2 note none tabrdc [m] read table (current page) to tblh and data memory 2 note none tabrdl [m] read table (last page) to tblh and data memory 2 note none miscellaneous nop no operation 1 none clr [m] clear data memory 1 note none set [m] set data memory 1 note none clr wdt clear watchdog timer 1 to, pdf clr wdt1 pre-clear watchdog timer 1 to, pdf clr wdt2 pre-clear watchdog timer 1 to, pdf swap [m] swap nibbles of data memory 1 note none swapa [m] swap nibbles of data memory with result in acc 1 none halt enter power down mode 1 to, pdf note: 1. for skip instructions, if the result of the comparison involves a skip then two cycles are required, if no skip takes place only one cycle is required. 2. any instruction which changes the contents of the pcl will also require 2 cycles for execution. 3. for the clr wdt1 and clr wdt2 instructions the t o and pdf flags may be af fected by the execution sta tus. t he t o a nd pdf fl ags a re c leared a fter bot h clr w dt1 a nd clr w dt2 instructions are consecutively executed. otherwise the t o and pdf fags remain unchanged.
rev. 1.11 78 april 11, 2017 rev. 1.11 79 april 11, 2017 HT45F56 shock detector flash mcu HT45F56 shock detector flash mcu instruction defnition adc a,[m] add d ata m emory to a cc w ith carry description the c ontents o f t he s pecifed d ata m emory, a ccumulator a nd t he c arry f ag a re a dded. the re sult is s tored in t he a ccumulator. operation acc a cc + [ m] + c affected f ag(s) ov, z , a c, c adcm a,[m] add a cc to d ata m emory w ith carry description the c ontents o f t he s pecifed d ata m emory, a ccumulator a nd t he c arry f ag a re a dded. the re sult is s tored in t he sp ecifed d ata m emory. operation [m] a cc + [ m] + c affected f ag(s) ov, z , a c, c add a,[m] add d ata m emory t o a cc description the c ontents o f t he s pecifed d ata m emory a nd t he a ccumulator a re a dded. the re sult is s tored in t he a ccumulator. operation acc a cc + [ m] affected f ag(s) ov, z , a c, c add a,x add im mediate data to a cc description the c ontents o f t he a ccumulator a nd t he s pecifed im mediate data a re a dded. the re sult is s tored in t he a ccumulator. operation acc a cc + x affected f ag(s) ov, z , a c, c addm a,[m] add a cc to d ata m emory description the c ontents o f t he s pecifed d ata m emory a nd t he a ccumulator a re a dded. the re sult is s tored in t he sp ecifed d ata m emory. operation [m] a cc + [ m] affected f ag(s) ov, z , a c, c and a,[m] logical a nd d ata m emory t o a cc description data i n t he a ccumulator a nd t he s pecifed d ata m emory p erform a b itwise l ogical a nd operation. t he re sult is s tored in t he a ccumulator. operation acc a cc a nd [ m] affected f ag(s) z and a,x logical a nd im mediate data to a cc description data i n t he a ccumulator a nd t he s pecifed im mediate data p erform a b it w ise l ogical a nd operation. t he re sult is s tored in t he a ccumulator. operation acc a cc a nd x affected f ag(s) z andm a,[m] logical a nd a cc to d ata m emory description data i n t he s pecifed d ata m emory a nd t he a ccumulator p erform a b itwise l ogical a nd operation. t he re sult is s tored in t he d ata m emory. operation [m] a cc and [ m] affected f ag(s) z
rev. 1.11 80 april 11, 2017 rev. 1.11 81 april 11, 2017 HT45F56 shock detector flash mcu HT45F56 shock detector flash mcu call addr subroutine c all description unconditionally c alls a s ubroutine a t t he s pecifed a ddress. th e p rogram c ounter t hen increments b y 1 to o btain t he a ddress o f t he n ext i nstruction w hich i s t hen p ushed o nto t he stack. t he sp ecifed a ddress is t hen loaded a nd t he p rogram c ontinues e xecution f rom t his new a ddress. a s t his instruction re quires a n a dditional op eration, it is a t wo c ycle instruction. operation stack p rogram counter + 1 program c ounter a ddr affected f ag(s) none clr [m] clear d ata m emory description each b it o f t he s pecifed d ata m emory i s cl eared t o 0 . operation [m] 00h affected f ag(s) none clr [m].i clear bi t o f d ata m emory description bit i o f t he s pecifed d ata m emory i s cl eared t o 0 . operation [m].i 0 affected f ag(s) none clr wdt clear w atchdog t imer description the t o, p df f ags a nd t he w dt a re al l c leared. operation wdt cl eared to 0 pdf 0 affected f ag(s) to, p df clr wdt1 pre-clear w atchdog t imer description the t o, p df f ags a nd t he w dt a re a ll c leared. n ote t hat t his instruction w orks in conjunction w ith c lr w dt2 a nd m ust b e e xecuted al ternately w ith c lr w dt2 to h ave effect. r epetitively e xecuting t his i nstruction w ithout al ternately e xecuting c lr w dt2 w ill have no e ffect. operation wdt cl eared to 0 pdf 0 affected f ag(s) to, p df clr wdt2 pre-clear w atchdog t imer description the t o, p df f ags and t he w dt are all cleared. n ote t hat t his i nstruction w orks i n conjunction with c lr w dt1 a nd m ust b e e xecuted al ternately w ith c lr w dt1 to h ave e ffect. r epetitively e xecuting t his i nstruction w ithout al ternately e xecuting c lr w dt1 w ill h ave n o e ffect. operation wdt cl eared to 0 pdf 0 affected f ag(s) to, p df cpl [m] complement d ata m emory description each b it of t he s pecifed d ata m emory i s l ogically complemented ( 1s complement). b its w hich previously c ontained a 1 a re c hanged to 0 a nd v ice v ersa. operation [m] [m] affected f ag(s) z
rev. 1.11 80 april 11, 2017 rev. 1.11 81 april 11, 2017 HT45F56 shock detector flash mcu HT45F56 shock detector flash mcu cpla [m] complement d ata m emory w ith r esult i n a cc description each b it of t he s pecifed d ata m emory i s l ogically complemented ( 1s complement). b its w hich previously c ontained a 1 a re c hanged to 0 a nd v ice v ersa. th e c omplemented r esult i s s tored i n the a ccumulator a nd t he c ontents o f t he d ata m emory r emain u nchanged. operation acc [ m] affected f ag(s) z daa [m] decimal-adjust a cc f or addition w ith r esult i n d ata m emory description convert t he c ontents o f t he a ccumulator v alue to a b cd ( binary c oded d ecimal) v alue resulting f rom t he p revious a ddition o f t wo b cd v ariables. i f t he low n ibble is greater t han 9 or i f a c f ag i s s et, t hen a v alue o f 6 w ill b e a dded to t he l ow n ibble. o therwise t he l ow n ibble remains u nchanged. i f t he h igh n ibble i s g reater t han 9 o r i f t he c f ag i s s et, t hen a v alue o f 6 will b e a dded to t he h igh n ibble. e ssentially, t he decimal c onversion i s p erformed b y a dding 00h, 0 6h, 6 0h o r 6 6h depending o n t he a ccumulator a nd f ag c onditions. o nly t he c f ag may b e a ffected b y t his instruction w hich indicates t hat if t he o riginal b cd s um is greater t han 100, it al lows m ultiple p recision decimal a ddition. operation [m] a cc + 00h or [m] a cc + 06 h o r [m] a cc + 60h o r [m] a cc + 66h affected f ag(s) c dec [m] decrement d ata m emory description data i n t he s pecifed d ata m emory i s d ecremented b y 1 . operation [m] [ m] ? 1 affected f ag(s) z deca [m] decrement d ata m emory wi th r esult i n a cc description data in t he sp ecifed d ata m emory is d ecremented b y 1 . t he re sult is s tored in t he accumulator. th e c ontents o f t he d ata m emory r emain u nchanged. operation acc [ m] ? 1 affected f ag(s) z halt enter p ower down m ode description this i nstruction s tops t he p rogram e xecution a nd t urns o ff t he s ystem c lock. th e c ontents o f the d ata m emory a nd r egisters a re r etained. th e w dt a nd p rescaler a re c leared. th e p ower down f ag p df i s s et a nd t he w dt t ime-out f ag t o i s c leared. operation to 0 pdf 1 affected f ag(s) to, p df inc [m] increment d ata m emory description data in t he sp ecifed d ata m emory is incremented b y 1 . operation [m] [ m] + 1 affected f ag(s) z inca [m] increment d ata m emory wi th r esult i n a cc description data i n t he sp ecifed d ata m emory i s i ncremented b y 1 . th e re sult i s s tored i n t he a ccumulator. the c ontents o f t he d ata m emory r emain u nchanged. operation acc [ m] + 1 affected f ag(s) z
rev. 1.11 82 april 11, 2017 rev. 1.11 83 april 11, 2017 HT45F56 shock detector flash mcu HT45F56 shock detector flash mcu jmp addr jump u nconditionally description the c ontents o f t he p rogram c ounter a re re placed w ith t he sp ecifed a ddress. p rogram execution t hen c ontinues f rom t his n ew a ddress. a s t his re quires t he insertion o f a d ummy instruction w hile t he n ew a ddress is loaded, it is a t wo c ycle instruction. operation program counter addr affected f ag(s) none mov a,[m] move d ata m emory t o a cc description the c ontents o f t he s pecifed d ata m emory a re c opied to t he a ccumulator. operation acc [ m] affected f ag(s) none mov a,x move im mediate data to a cc description the im mediate data s pecifed i s l oaded i nto t he a ccumulator. operation acc x affected f ag(s) none mov [m],a move a cc to d ata m emory description the c ontents o f t he a ccumulator a re c opied to t he s pecifed d ata m emory. operation [m] a cc affected f ag(s) none nop no o peration description no o peration i s p erformed. e xecution c ontinues w ith t he n ext i nstruction. operation no operation affected f ag(s) none or a,[m] logical o r d ata m emory to a cc description data i n t he a ccumulator a nd t he s pecifed d ata m emory p erform a b itwise logical o r op eration. t he re sult is s tored in t he a ccumulator. operation acc a cc or [ m] affected f ag(s) z or a,x logical or im mediate data to a cc description data i n t he a ccumulator a nd t he s pecifed im mediate data p erform a b itwise l ogical o r operation. t he re sult is s tored in t he a ccumulator. operation acc a cc or x affected f ag(s) z orm a,[m] logical or a cc to d ata m emory description data i n t he s pecifed d ata m emory a nd t he a ccumulator p erform a b itwise l ogical o r operation. t he re sult is s tored in t he d ata m emory. operation [m] a cc or [ m] affected f ag(s) z ret return from s ubroutine description the p rogram c ounter is re stored f rom t he s tack. p rogram e xecution c ontinues a t t he re stored a ddress. operation program counter s tack affected f ag(s) none
rev. 1.11 82 april 11, 2017 rev. 1.11 83 april 11, 2017 HT45F56 shock detector flash mcu HT45F56 shock detector flash mcu ret a,x return f rom su broutine and l oad im mediate data to a cc description the p rogram c ounter i s r estored f rom t he s tack a nd t he a ccumulator l oaded w ith t he s pecifed immediate data. p rogram e xecution c ontinues a t t he r estored a ddress. operation program counter s tack acc x affected f ag(s) none reti return from i nterrupt description the p rogram c ounter is re stored f rom t he s tack a nd t he interrupts a re re -enabled b y s etting t he emi b it. e mi i s t he m aster i nterrupt g lobal e nable b it. i f a n i nterrupt w as p ending w hen t he reti instruction is e xecuted, t he p ending in terrupt ro utine w ill b e p rocessed b efore re turning to t he m ain p rogram. operation program counter s tack emi 1 affected f ag(s) none rl [m] rotate d ata m emory l eft description the c ontents o f t he s pecifed d ata m emory a re r otated l eft b y 1 b it w ith b it 7 r otated i nto b it 0 . operation [m].(i+1) [ m].i; (i=0~6) [m].0 [ m].7 affected f ag(s) none rla [m] rotate d ata m emory left w ith re sult in a cc description the c ontents o f t he s pecifed d ata m emory a re r otated l eft b y 1 b it w ith b it 7 r otated i nto b it 0 . the r otated r esult i s s tored i n t he a ccumulator a nd t he c ontents o f t he d ata m emory r emain u nchanged. operation acc.(i+1) [ m].i; (i=0~6) acc.0 [ m].7 affected f ag(s) none rlc [m] rotate d ata m emory l eft t hrough carry description the c ontents o f t he s pecifed d ata m emory a nd t he c arry f ag a re r otated l eft b y 1 b it. b it 7 replaces t he c arry b it a nd t he o riginal c arry f ag i s r otated i nto b it 0 . operation [m].(i+1) [ m].i; (i=0~6) [m].0 c c [ m].7 affected f ag(s) c rlca [m] rotate d ata m emory left t hrough c arry w ith re sult in a cc description data i n t he s pecifed d ata m emory and t he carry f ag are r otated l eft b y 1 b it. b it 7 r eplaces t he carry b it a nd t he o riginal c arry f ag i s r otated i nto t he b it 0 . th e r otated r esult i s s tored i n t he accumulator a nd t he c ontents o f t he d ata m emory r emain u nchanged. operation acc.(i+1) [ m].i; (i=0~6) acc.0 c c [ m].7 affected f ag(s) c rr [m] rotate d ata m emory r ight description the contents of t he s pecifed d ata m emory are r otated r ight b y 1 b it w ith b it 0 r otated i nto b it 7 . operation [m].i [ m].(i+1); (i=0~6) [m].7 [ m].0 affected f ag(s) none
rev. 1.11 84 april 11, 2017 rev. 1.11 85 april 11, 2017 HT45F56 shock detector flash mcu HT45F56 shock detector flash mcu rra [m] rotate d ata m emory right with result i n a cc description data i n t he s pecifed d ata m emory a nd t he c arry f ag a re r otated r ight b y 1 b it w ith b it 0 rotated i nto b it 7 . th e r otated r esult i s s tored i n t he a ccumulator a nd t he c ontents o f t he data m emory r emain u nchanged. operation acc.i [ m].(i+1); (i=0~6) acc.7 [ m].0 affected f ag(s) none rrc [m] rotate d ata m emory r ight t hrough carry description the c ontents o f t he s pecifed d ata m emory a nd t he c arry f ag a re r otated r ight b y 1 b it. b it 0 replaces t he c arry b it a nd t he o riginal c arry f ag i s r otated i nto b it 7 . operation [m].i [ m].(i+1); (i=0~6) [m].7 c c [ m].0 affected f ag(s) c rrca [m] rotate d ata m emory right th rough c arry with result i n a cc description data i n t he s pecifed d ata m emory a nd t he c arry f ag a re r otated r ight b y 1 b it. b it 0 r eplaces the c arry b it a nd t he o riginal c arry f ag i s r otated i nto b it 7 . th e r otated r esult i s s tored i n t he accumulator a nd t he c ontents o f t he d ata m emory r emain u nchanged. operation acc.i [ m].(i+1); (i=0~6) acc.7 c c [ m].0 affected f ag(s) c sbc a,[m] subtract d ata m emory from a cc wi th c arry description the c ontents o f t he s pecifed d ata m emory a nd t he c omplement o f t he c arry f ag a re subtracted f rom t he a ccumulator. t he re sult is s tored in t he a ccumulator. n ote t hat if t he result o f s ubtraction is n egative, t he c f ag w ill b e c leared t o 0 , o therwise if t he re sult is positive o r z ero, t he c f ag w ill b e s et to 1 . operation acc a cc ? [ m] ? c affected f ag(s) ov, z , a c, c sbcm a,[m] subtract d ata m emory from a cc wi th c arry a nd r esult i n d ata m emory description the c ontents o f t he s pecifed d ata m emory a nd t he c omplement o f t he c arry f ag a re subtracted f rom t he a ccumulator. t he re sult is s tored in t he d ata m emory. n ote t hat if t he result o f s ubtraction is n egative, t he c f ag w ill b e c leared t o 0 , o therwise if t he re sult is positive o r z ero, t he c f ag w ill b e s et to 1 . operation [m] a cc ? [ m] ? c affected f ag(s) ov, z , a c, c sdz [m] skip i f decrement d ata m emory i s 0 description the c ontents o f t he s pecifed d ata m emory a re fr st decremented b y 1 . i f t he r esult i s 0 t he following instruction is s kipped. a s t his re quires t he insertion o f a d ummy instruction w hile the n ext instruction is f etched, it is a t wo c ycle instruction. i f t he re sult is n ot 0 t he p rogram proceeds w ith t he f ollowing i nstruction. operation [m] [ m] ? 1 skip if [ m]=0 affected f ag(s) none
rev. 1.11 84 april 11, 2017 rev. 1.11 85 april 11, 2017 HT45F56 shock detector flash mcu HT45F56 shock detector flash mcu sdza [m] skip i f decrement d ata m emory i s z ero w ith r esult i n a cc description the c ontents o f t he s pecifed d ata m emory a re fr st decremented b y 1 . i f t he r esult i s 0 , t he following instruction is s kipped. t he re sult is s tored in t he a ccumulator b ut t he sp ecifed data m emory c ontents r emain u nchanged. a s t his r equires t he i nsertion o f a dummy instruction w hile t he n ext instruction is f etched, it is a t wo c ycle instruction. i f t he r esult is n ot 0 , the p rogram p roceeds w ith t he f ollowing instruction. operation acc [ m] ? 1 skip if a cc=0 affected f ag(s) none set [m] set d ata m emory description each b it o f t he s pecifed d ata m emory i s s et t o 1 . operation [m] f fh affected f ag(s) none set [m].i set b it o f d ata m emory description bit i o f t he s pecifed d ata m emory i s s et t o 1 . operation [m].i 1 affected f ag(s) none siz [m] skip i f i ncrement d ata m emory i s 0 description the c ontents o f t he sp ecifed d ata m emory a re f rst incremented b y 1 . i f t he re sult is 0 , t he following instruction is s kipped. a s t his re quires t he insertion o f a d ummy instruction w hile the n ext instruction is f etched, it is a t wo c ycle instruction. i f t he re sult is n ot 0 t he p rogram proceeds w ith t he f ollowing i nstruction. operation [m] [ m] + 1 skip if [ m]=0 affected f ag(s) none siza [m] skip if increment d ata m emory is z ero w ith re sult in a cc description the c ontents o f t he sp ecifed d ata m emory a re f rst incremented b y 1 . i f t he re sult is 0 , t he following instruction is s kipped. t he re sult is s tored in t he a ccumulator b ut t he sp ecifed data m emory c ontents r emain u nchanged. a s t his r equires t he i nsertion o f a dummy instruction w hile t he n ext instruction is f etched, it is a t wo c ycle instruction. i f t he re sult is n ot 0 t he p rogram p roceeds w ith t he f ollowing instruction. operation acc [ m] + 1 skip if a cc=0 affected f ag(s) none snz [m].i skip i f b it i of d ata m emory i s n ot 0 description if b it i o f t he sp ecifed d ata m emory is n ot 0 , t he f ollowing instruction is s kipped. a s t his requires t he insertion o f a d ummy instruction w hile t he n ext instruction is f etched, it is a t wo cycle instruction. i f t he re sult is 0 t he p rogram p roceeds w ith t he f ollowing instruction. operation skip i f [ m].i 0 affected f ag(s) none sub a,[m] subtract d ata m emory from a cc description the s pecifed d ata m emory i s s ubtracted f rom t he c ontents o f t he a ccumulator. th e r esult i s stored in t he a ccumulator. n ote t hat if t he re sult o f s ubtraction is n egative, t he c f ag w ill b e cleared to 0 , o therwise i f t he r esult i s p ositive o r z ero, t he c f ag w ill b e s et to 1 . operation acc a cc ? [ m] affected f ag(s) ov, z , a c, c
rev. 1.11 86 april 11, 2017 rev. 1.11 87 april 11, 2017 HT45F56 shock detector flash mcu HT45F56 shock detector flash mcu subm a,[m] subtract d ata m emory from a cc wi th r esult i n d ata m emory description the s pecifed d ata m emory i s s ubtracted f rom t he c ontents o f t he a ccumulator. th e r esult i s stored in t he d ata m emory. n ote t hat if t he re sult o f s ubtraction is n egative, t he c f ag w ill b e cleared to 0 , o therwise i f t he r esult i s p ositive o r z ero, t he c f ag w ill b e s et to 1 . operation [m] a cc ? [ m] affected f ag(s) ov, z , a c, c sub a,x subtract im mediate data f rom a cc description the im mediate data s pecifed b y t he c ode i s s ubtracted f rom t he c ontents o f t he a ccumulator. the re sult is s tored in t he a ccumulator. n ote t hat if t he re sult o f s ubtraction is n egative, t he c fag w ill b e c leared to 0 , o therwise i f t he r esult i s p ositive o r z ero, t he c f ag w ill b e s et to 1 . operation acc a cc ? x affected f ag(s) ov, z , a c, c swap [m] swap ni bbles of d ata m emory description the l ow-order a nd h igh-order n ibbles o f t he s pecifed d ata m emory a re i nterchanged. operation [m].3~[m].0 ? [ m].7~[m].4 affected f ag(s) none swapa [m] swap ni bbles of d ata m emory w ith r esult i n a cc description the l ow-order a nd h igh-order n ibbles o f t he s pecifed d ata m emory a re i nterchanged. th e result i s s tored i n t he a ccumulator. th e c ontents o f t he d ata m emory r emain u nchanged. operation acc.3~acc.0 [ m].7~[m].4 acc.7~acc.4 [ m].3~[m].0 affected f ag(s) none sz [m] skip i f d ata m emory i s 0 description if t he contents of t he s pecifed d ata m emory i s 0, t he following i nstruction i s s kipped. a s t his requires t he insertion o f a d ummy instruction w hile t he n ext instruction is f etched, it is a t wo cycle instruction. i f t he re sult is n ot 0 t he p rogram p roceeds w ith t he f ollowing instruction. operation skip if [ m]=0 affected f ag(s) none sza [m] skip i f d ata m emory i s 0 w ith data m ovement to a cc description the c ontents o f t he s pecifed d ata m emory a re c opied to t he a ccumulator. i f t he v alue i s z ero, the f ollowing instruction is s kipped. a s t his re quires t he insertion o f a d ummy instruction while t he n ext instruction is f etched, it is a t wo c ycle instruction. i f t he re sult is n ot 0 t he program p roceeds w ith t he f ollowing instruction. operation acc [ m] skip if [ m]=0 affected f ag(s) none sz [m].i skip i f b it i of d ata m emory i s 0 description if b it i o f t he sp ecifed d ata m emory is 0 , t he f ollowing instruction is s kipped. a s t his re quires the insertion o f a d ummy instruction w hile t he n ext instruction is f etched, it is a t wo c ycle instruction. i f t he re sult is n ot 0 , t he p rogram p roceeds w ith t he f ollowing instruction. operation skip if [ m].i=0 affected f ag(s) none
rev. 1.11 86 april 11, 2017 rev. 1.11 87 april 11, 2017 HT45F56 shock detector flash mcu HT45F56 shock detector flash mcu tabrd [m] read ta ble ( specifc p age) to t blh a nd d ata m emory description the low b yte o f t he p rogram c ode ( specifc p age) a ddressed b y t he t able p ointer p air (tbhp a nd t blp) i s mo ved t o t he s pecifed d ata m emory a nd t he h igh by te mo ved t o t blh. operation [m] pr ogram c ode (low by te) tblh pr ogram c ode (high by te) affected f ag(s) none tabrdc [m] read ta ble ( current p age) to t blh a nd d ata m emory description the low b yte o f t he p rogram c ode ( current p age) a ddressed b y t he t able p ointer ( tblp) is moved t o t he s pecifed d ata m emory a nd t he h igh by te mo ved t o t blh. operation [m] pr ogram c ode (low by te) tblh pr ogram c ode (high by te) affected f ag(s) none tabrdl [m] read t able (last p age) t o t blh a nd d ata m emory description the l ow by te o f t he pr ogram c ode (last p age) a ddressed by t he t able p ointer (tblp) i s mo ved to t he s pecifed d ata m emory a nd t he h igh b yte m oved to t blh. operation [m] pr ogram c ode (low by te) tblh pr ogram c ode (high by te) affected f ag(s) none xor a,[m] logical x or d ata m emory to a cc description data i n t he a ccumulator a nd t he s pecifed d ata m emory p erform a b itwise l ogical x or operation. t he re sult is s tored in t he a ccumulator. operation acc a cc x or [ m] affected f ag(s) z xorm a,[m] logical x or a cc to d ata m emory description data i n t he s pecifed d ata m emory a nd t he a ccumulator p erform a b itwise l ogical x or operation. t he re sult is s tored in t he d ata m emory. operation [m] a cc xor [ m] affected f ag(s) z xor a,x logical x or im mediate data to a cc description data i n t he a ccumulator a nd t he s pecifed im mediate data p erform a b itwise l ogical x or operation. t he re sult is s tored in t he a ccumulator. operation acc a cc x or x affected f ag(s) z
rev. 1.11 88 april 11, 2017 rev. 1.11 89 april 11, 2017 HT45F56 shock detector flash mcu HT45F56 shock detector flash mcu package information note that the package information provided here is for consultation purposes only . as this information may be updated at regular intervals users are reminded to consult the holtek website for the latest version of the package/carton information . additional supplementary information with regard to pa ckaging is listed below. click on the relevant section to be transferred to the relevant website page. ? further package information (include outline dimensions, product t ape and reel specifcations) ? packing meterials information ? carton information
rev. 1.11 88 april 11, 2017 rev. 1.11 89 april 11, 2017 HT45F56 shock detector flash mcu HT45F56 shock detector flash mcu 8-pin sop (150mil) outline dimensions symbol dimensions in inch min. nom. max. a 0.236 bsc b 0.154 bsc c 0.012 0.020 c 0.193 bsc d 0.069 e 0.050 bsc f 0.004 0.010 g 0.016 0.050 h 0.004 0.010 0 8 symbol dimensions in mm min. nom. max. a 6 bsc b 3.9 bsc c 0.31 0.51 c 4.9 bsc d 1.75 e 1.27 bsc f 0.10 0.25 g 0.40 1.27 h 0.10 0.25 0 8
rev. 1.11 90 april 11, 2017 rev. 1.11 pb april 11, 2017 HT45F56 shock detector flash mcu HT45F56 shock detector flash mcu copyright ? 2017 by holtek semiconductor inc. the information appearing in this data sheet is believed to be accurate at the time of publication. however, holtek assumes no responsibility arising from the use of the specifcations described. the applications mentioned herein are used solely for the purpose of illustration and holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. holtek's products are not authorized for use as critical components in life support devices or systems. holtek reserves the right to alter its products without prior notifcation. for the most up-to-date information, please visit our web site at http://www.holtek.com.tw.

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